build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )
Change subject: Add configurable ramstage support for minimal PCI scanning
......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36221/2/src/include/device/device.h
File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/36221/2/src/include/device/device.h...
PS2, Line 132: unsigned int mandatory : 1; /* set if this device is used even in minimum PCI cases */
line over 96 characters
https://review.coreboot.org/c/coreboot/+/36221/2/util/sconfig/lex.yy.c_shipp...
File util/sconfig/lex.yy.c_shipped:
https://review.coreboot.org/c/coreboot/+/36221/2/util/sconfig/lex.yy.c_shipp...
PS2, Line 162:
trailing whitespace
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Gerrit-Change-Number: 36221
Gerrit-PatchSet: 2
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Gerrit-Comment-Date: Tue, 22 Oct 2019 05:34:32 +0000
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