[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8186: Correct SPI_HZ for PLL

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin.
Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59939 )

Change subject: soc/mediatek/mt8186: Correct SPI_HZ for PLL
......................................................................

soc/mediatek/mt8186: Correct SPI_HZ for PLL

The SPI speed is 218.4MHz, so correct the value of SPI_HZ.

BUG=b:202871018
TEST=build pass

Signed-off-by: Rex-BC Chen 
Change-Id: I6e8ba10a851e1507405cdd41939a176462734487
---
M src/soc/mediatek/mt8186/include/soc/pll.h
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/59939/1

diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h
index ce98077..c2dace3 100644
--- a/src/soc/mediatek/mt8186/include/soc/pll.h
+++ b/src/soc/mediatek/mt8186/include/soc/pll.h
@@ -492,12 +492,12 @@
 /* top_div rate */
 enum {
    CLK26M_HZ	= 26 * MHz,
-	UNIVPLL_D6_D2_HZ = UNIV2PLL_HZ / 2 / 6 / 2,
+	MAINPLL_D5_HZ = MAINPLL_HZ / 5,
 };

/* top_mux rate */
 enum {
-	SPI_HZ		= UNIVPLL_D6_D2_HZ,
+	SPI_HZ		= MAINPLL_D5_HZ,
    UART_HZ		= CLK26M_HZ,
 };