Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48153 )
Change subject: soc/intel/alderlake: Align chipset.cb with pci_devs.h ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48153/2/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/48153/2/src/soc/intel/alderlake/chi... PS2, Line 16: tcss_xhci off end : device pci 0d.1 alias tcss_xdci off end : device pci 0d.2 alias tcss_dma0 off end : device pci 0d.3 alias tcss_dma1 off end I was using the convention from soc/intel/tigerlake/chipset.cb, WDYT?
https://review.coreboot.org/c/coreboot/+/48153/2/src/soc/intel/alderlake/chi... PS2, Line 22: device pci 10.1 alias thc1 off end : device pci 10.2 alias cnvi_bt off end I thought it seemed weird, but the EDS version I have (#630094, august 2020, rev 0.7) says functions 6 and 7 ... which would be another PCI bus violation, w/o a function 0. What version of the EDS do you have?