[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add macros and SPD information for DDR4

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
PS2, Line 25: #define DDR4_DIMM_SLOTS	(DIMMS_PER_CHANNEL * DDR4_CHANNELS)
> nits: one more tab, align with above.

Done

https://review.coreboot.org/c/coreboot/+/39866/2/src/soc/intel/tigerlake/inc... 
PS2, Line 29: /* Supports reading SPD using SMBus. */
> nit: line these comments up with MEMORY_DOWN

Done