[coreboot-gerrit] Change in coreboot[master]: cpu/x86/lapic: Only deliver ExtINT to BSP

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Felix Held.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42434 )

Change subject: cpu/x86/lapic: Only deliver ExtINT to BSP
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Patch Set 13:

(1 comment)

File src/cpu/x86/lapic/lapic.c:

https://review.coreboot.org/c/coreboot/+/42434/comment/4c5f2b78_966be864 
PS5, Line 45: 		);
> Turning it into a question: If we don't want LVT0 on APs, why do we want […]

Regarding spec B.1, PARALLEL_MP will send some IPIs and only some CPU models return to wait for INIT/STARTUP IPI state. So APs can enter NMI handler. I would have assumed that any NMI signal connected to LINT1 pins would be shared between CPUs, so delivering it to APs too would sounds like correct thing to do. It's closer to the state prior to enabling the LAPIC, while there is still possibility NMI handler is not installed at all.

For ExtINT SDK says that it should be routed to one CPU only. I think legacy PIC i8259 controller gets confused otherwise.