Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44512 )
Change subject: soc/intel/common: Call pci_dev_request_bus_master() from .final ops ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44512/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44512/2//COMMIT_MSG@15 PS2, Line 15: access Thanks for the detailed inputs, Nico! They are helpful to understand the history here.
Yes, but mostly by accident. To my knowledge, there are historically three cases when we enable bus mastering:
If that is the case, I think we should fix coreboot to not enable the bus mastering for any of these devices which don't need it at least in the early initialization sequence.
I read about it. What payload was that actually?
Ran into this with depthcharge. However, if the spec we want to enforce in coreboot is to not enable bus mastering for payloads, then I can look into following up on getting this fixed in depthcharge.
There may be more than a single chip on the mainboard. And not everything soldered to a mainboard has the same level of trust.
Agreed.
That aside, we have already tested minimal bus master settings.
Are there more details that you can share about the minimal bus master settings? What devices and platforms were tested and if there were settings identified in coreboot that are clearly wrong. I agree with what you said above - if these are really not required within coreboot, I think we should clean those up rather than adding more quirks.
Subrata - is this something you can follow up on?