EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 23: RP_1
Probably add PCH_ as a prefix to indicate these are PCH PCIE RP numbers? And we would also need: […]
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 39: SRC_1 = (1 << 0),
This is not required. […]
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 54: enum pcie_rp_type {
This can be moved to fsp_params.c since it is only used in that file.
Done