Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32788 )
Change subject: soc/intel/common/block/gpio: Add gpio_pm_configure() function
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Patch Set 7:
(3 comments)
https://review.coreboot.org/#/c/32788/7/src/soc/intel/common/block/gpio/gpio...
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/32788/7/src/soc/intel/common/block/gpio/gpio...
PS7, Line 618: 0x3f
Agree with Furquan's comment. […]
Done
https://review.coreboot.org/#/c/32788/7/src/soc/intel/common/block/gpio/gpio...
PS7, Line 618: 0x3f
Define this as a macro along with the rest of MISCCFG_* you are adding in gpio. […]
Done
https://review.coreboot.org/#/c/32788/7/src/soc/intel/common/block/gpio/gpio...
PS7, Line 627: pcr_rmw8
GPIO_MISCCFG is a 32-bit register. […]
i don't see any such strict recommendation about 32 bit read alone
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I816a70ad92595f013740a235a9799912ad51665e
Gerrit-Change-Number: 32788
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