Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37115 )
Change subject: sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode ......................................................................
Patch Set 24:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37115/24/src/southbridge/intel/bd82... File src/southbridge/intel/bd82x6x/me.c:
https://review.coreboot.org/c/coreboot/+/37115/24/src/southbridge/intel/bd82... PS24, Line 246: 20 sec twenty seconds? Why stall for so long?
https://review.coreboot.org/c/coreboot/+/37115/5/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/me_8.x.c:
https://review.coreboot.org/c/coreboot/+/37115/5/src/southbridge/intel/bd82x... PS5, Line 523: struct device *lpc = pcidev_on_root(0x1f, 0); : u32 etr3 = pci_read_config32(lpc, ETR3)
i hope it's not, marking as resolved.
The thing about pcidev_on_root() is that it could return NULL. `config_of` couldn't be used here, though
https://review.coreboot.org/c/coreboot/+/37115/24/src/southbridge/intel/bd82... File src/southbridge/intel/bd82x6x/me_8.x.c:
https://review.coreboot.org/c/coreboot/+/37115/24/src/southbridge/intel/bd82... PS24, Line 223: 20 sec Wait, isn't the code in this file the same as on me.c?