[coreboot-gerrit] Change in coreboot[master]: mb/prodrive/hermes: Correct memory RCOMP settings

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58364 )

Change subject: mb/prodrive/hermes: Correct memory RCOMP settings
......................................................................

mb/prodrive/hermes: Correct memory RCOMP settings

The original RCOMP resistor and target values only apply to ULT CPUs and
do not make sense for the CFL-S CPUs Hermes uses. Fix the RCOMP settings
and the associated comments.

Tested, still boots.

Change-Id: I015797c58c914c6581d472e6d70d2dd7bad2b14f
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58364
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/mainboard/prodrive/hermes/romstage.c
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c
index 513bab3..b52c52c 100644
--- a/src/mainboard/prodrive/hermes/romstage.c
+++ b/src/mainboard/prodrive/hermes/romstage.c
@@ -24,11 +24,11 @@
    	.spd_spec = {.spd_smbus_address = 0xa6}
    },

-	/* Baseboard uses 121, 81 and 100 rcomp resistors */
-	.rcomp_resistor = {121, 81, 100},
+	/* Rcomp resistors on CFL-S are located on the CPU itself */
+	.rcomp_resistor = {121, 75, 100},

-	/* Baseboard Rcomp target values. */
-	.rcomp_targets = {100, 40, 20, 20, 26},
+	/* Rcomp target values for CFL-S, DDR4 and 2 DIMMs per channel */
+	.rcomp_targets = {60, 26, 20, 20, 26},

/* Baseboard is an interleaved design */
    .dq_pins_interleaved = 1,