Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4846
-gerrit
commit 47c1725d496c0245abd6534e3d3395bfadc348f9 Author: Aaron Durbin adurbin@chromium.org Date: Mon Jan 27 16:39:17 2014 -0600
x86/mtrr: don't assume size of ROM cached during CAR mode
Romstage and ramstage can use 2 different values for the amount of ROM to cache just under 4GiB in the address space. Don't assume a cpu's romstage caching policy for the ROM.
Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/include/cpu/x86/mtrr.h | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bbcde8a..9414687 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -134,10 +134,6 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type);
#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
-#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL) -# error "CAR region (WB) and flash (WP) regions overlap." -#endif - #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif