Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82656?usp=email )
Change subject: util/autoport: Update for two recent USB developments ......................................................................
util/autoport: Update for two recent USB developments
Update autoport for:
1. Commit xxxxxxxxxxxx ("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge") 2. Commit xxxxxxxxxxxx ("sb/intel/bd82x6x: Allow actual USBIRx values in devicetree")
As a side effect of #2 above, no more FIXME comment (which was broken anyway) will be written for usb_port_config.
Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3 Signed-off-by: Keith Hui buurin@gmail.com --- M util/autoport/bd82x6x.go 1 file changed, 39 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82656/1
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 76411e7..fdb40d8 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -271,37 +271,7 @@ cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4]) }
- PutPCIChip(addr, cur) - PutPCIDevParent(addr, "", "lpc") - - DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/common/acpi/platform.asl", - }) - DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", - }) - DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/common/acpi/sleepstates.asl", - }) - DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ - File: "southbridge/intel/bd82x6x/acpi/pch.asl", - }) - - AddBootBlockFile("early_init.c", "") - AddROMStageFile("early_init.c", "") - - sb := Create(ctx, "early_init.c") - defer sb.Close() - Add_gpl(sb) - - sb.WriteString(` -#include <bootblock_common.h> -#include <device/pci_ops.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <southbridge/intel/bd82x6x/pch.h> - -`) - sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") + usbPortConfig := "{\n"
currentMap := map[uint32]int{ 0x20000153: 0, @@ -332,19 +302,48 @@ } } current, ok := currentMap[inteltool.RCBA[uint16(0x3500+4*port)]] - comment := "" if !ok { - comment = fmt.Sprintf("// FIXME: Unknown current: RCBA(0x%x)=0x%x", 0x3500+4*port, uint16(0x3500+4*port)) + usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, 0x%x, %d},\n", + ((inteltool.RCBA[0x359c]>>port)&1)^1, + inteltool.RCBA[uint16(0x3500+4*port)] & 0xfff, + OCPin) + } else { + usbPortConfig += fmt.Sprintf("\t\t\t\t{%d, %d, %d},\n", + ((inteltool.RCBA[0x359c]>>port)&1)^1, + current, + OCPin) } - fmt.Fprintf(sb, "\t{ %d, %d, %d }, %s\n", - ((inteltool.RCBA[0x359c]>>port)&1)^1, - current, - OCPin, - comment) } - sb.WriteString("};\n") + usbPortConfig += "\t\t\t}" + cur.Registers["usb_port_config"] = usbPortConfig
- guessedMap := GuessSPDMap(ctx) + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/common/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/bd82x6x/acpi/pch.asl", + }) + + AddBootBlockFile("early_init.c", "") + AddROMStageFile("early_init.c", "") + + sb := Create(ctx, "early_init.c") + defer sb.Close() + Add_gpl(sb) + + sb.WriteString(` +#include <bootblock_common.h> +#include <device/pci_ops.h> +`)
sb.WriteString(` void bootblock_mainboard_early_init(void) @@ -354,15 +353,6 @@
RestorePCI16Simple(sb, addr, 0x80)
- sb.WriteString(`} - -/* FIXME: Put proper SPD map here. */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ -`) - for i, spd := range guessedMap { - fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd) - } sb.WriteString("}\n")
gnvs := Create(ctx, "acpi_tables.c")