John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46504 )
Change subject: Fix memory corruptions ......................................................................
Fix memory corruptions
Coverity detects source memory is overrun. Fix this issue by using the correct source memory size to avoid memory corruption.
Found-by: Coverity CID 1429762 1429774 TEST=None
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/46504/1
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index d66e890a..fe7641f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -355,14 +355,14 @@
memcpy(params->PcieRpAdvancedErrorReporting, config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); + sizeof(config->PcieRpAdvancedErrorReporting));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented, sizeof(config->PcieRpSlotImplemented)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(params->PcieRpHotPlug)); + sizeof(config->PcieRpHotPlug));
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];