Maximilian Schander has uploaded this change for review. ( https://review.coreboot.org/22350
Change subject: util/inteltool: Add PCIEXBAR and PXPEPBAR reading for skylake ......................................................................
util/inteltool: Add PCIEXBAR and PXPEPBAR reading for skylake
Both registers behave the same as on the previous generation
Taken from * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2 * Page 55 and 62 * 332688-003EN
Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9 Signed-off-by: Maximilian Schander coreboot@mimoja.de --- M util/inteltool/pcie.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/22350/1
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index e8b8c94..ac76bd6 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -280,6 +280,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -501,6 +503,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break;