[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Update thermal configuration for DPTF

[John Su (Code Review)]

John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31170 )

Change subject: mb/google/sarien/variants/sarien: Update thermal configuration for DPTF
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Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/31170/5/src/mainboard/google/sarien/variants... 
File src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl:

https://review.coreboot.org/#/c/31170/5/src/mainboard/google/sarien/variants... 
PS5, Line 42: 5000
> I am not clear on this. Please, explain why this is such a high number.

Setting 5000 for CPU Influence(mw), because this is our test result, due to CPU at performance behavior will arise to 51W, and it will meet to Tcc offset 5 & PSV95, so we need set CPU 5000 Influence(mw) to quickly pull down power, thanks.

https://review.coreboot.org/#/c/31170/5/src/mainboard/google/sarien/variants... 
PS5, Line 67: 3000
> How did you arrive to this number ? I would suggest to keep this at least same as PL1 minimum i.e. […]

Set PL1 MIN 3000 is for skin test, when we test high temperature ambient, we want CPU power get lower to avoid system skin test fail, and 3000 is the best that our result, thanks.