David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71628 )
Change subject: mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC ......................................................................
mb/google/brya/var/kano: Set the ov2740 to 0 and the hi556 to 1 for SSFC
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, it will treat missing SSFC as zero, so Kano needs to set the ov2740 to 0 to avoid probing wrong mipi camera.
Before patch
fw_config match found: UFC=UFC_MIPI_OVTI2740 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: UFC=UFC_MIPI_OVTI2740 fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556 fw_config match found: UFC=UFC_MIPI_OVTI2740 fw_config match found: STYLUS=STYLUS_PRESENT
After patch
fw_config match found: UFC=UFC_MIPI_OVTI2740 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S fw_config match found: UFC=UFC_MIPI_OVTI2740 I2C: 00:20 disabled by fw_config fw_config match found: UFC=UFC_MIPI_OVTI2740 fw_config match found: STYLUS=STYLUS_PRESENT
BUG=b:262939431 TEST=Boot on kano and check functional with ov2740 camera.
Change-Id: I46fac6c820d6006956680a07198db82225630905 Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 39 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/71628/1
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index b45fbf7..f1fe5e7 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -17,8 +17,8 @@ option STYLUS_PRESENT 1 end field ZYDRON_UFC 36 37 - option UFC_MIPI_HI556 0 - option UFC_MIPI_OVTI2740 1 + option UFC_MIPI_OVTI2740 0 + option UFC_MIPI_HI556 1 end end chip soc/intel/alderlake