Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77229?usp=email )
Change subject: soc/intel/common/block: Share Intel Graphics Device init function ......................................................................
soc/intel/common/block: Share Intel Graphics Device init function
This patch extracts and shares the early_graphics.c::device_init() function to make it avaiable for other use.
The igd_init() function enables MMIO and port IO of the Intel Graphics Device and program the Base Address Range 0 according to the `CONFIG_GFX_GMA_DEFAULT_MMIO' configuration element.
BUG=b:279173035 TEST=No impact on a skolas board using this function
Change-Id: I8197a2baffe45eadceeb0ac349cde8ae2a9b41a0 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/soc/intel/common/block/graphics/Makefile.inc M src/soc/intel/common/block/graphics/early_graphics.c A src/soc/intel/common/block/graphics/igd_init.c A src/soc/intel/common/block/include/intelblocks/igd_init.h 4 files changed, 36 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/77229/1
diff --git a/src/soc/intel/common/block/graphics/Makefile.inc b/src/soc/intel/common/block/graphics/Makefile.inc index ac053de..b032cae 100644 --- a/src/soc/intel/common/block/graphics/Makefile.inc +++ b/src/soc/intel/common/block/graphics/Makefile.inc @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += early_graphics.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += igd_init.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS) += graphics.c diff --git a/src/soc/intel/common/block/graphics/early_graphics.c b/src/soc/intel/common/block/graphics/early_graphics.c index c8a1d84..e9d7ea1 100644 --- a/src/soc/intel/common/block/graphics/early_graphics.c +++ b/src/soc/intel/common/block/graphics/early_graphics.c @@ -3,24 +3,10 @@ #include <device/pci.h> #include <drivers/intel/gma/libgfxinit.h> #include <intelblocks/early_graphics.h> +#include <intelblocks/igd_init.h> #include <soc/gpio.h> #include <soc/pci_devs.h>
-static void device_init(void) -{ - /* Disable response in IO and MMIO space. */ - pci_and_config16(SA_DEV_IGD, PCI_COMMAND, - ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); - - /* Program IGD Base Address Register 0. */ - pci_write_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0, - CONFIG_GFX_GMA_DEFAULT_MMIO); - - /* Enable response in IO and MMIO space. */ - pci_or_config16(SA_DEV_IGD, PCI_COMMAND, - (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); -} - __weak const struct pad_config *variant_early_graphics_gpio_table(size_t *num) { *num = 0; @@ -37,7 +23,7 @@ return false;
/* Perform minimal graphic MMIO configuration. */ - device_init(); + igd_init();
/* Optionally configure any required display related GPIOs */ pads = variant_early_graphics_gpio_table(&pads_num); diff --git a/src/soc/intel/common/block/graphics/igd_init.c b/src/soc/intel/common/block/graphics/igd_init.c new file mode 100644 index 0000000..d6bfd801 --- /dev/null +++ b/src/soc/intel/common/block/graphics/igd_init.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci.h> +#include <intelblocks/igd_init.h> +#include <soc/pci_devs.h> + +void igd_init(void) +{ + /* Disable response in IO and MMIO space. */ + pci_and_config16(SA_DEV_IGD, PCI_COMMAND, + ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); + + /* Program IGD Base Address Register 0. */ + pci_write_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0, + CONFIG_GFX_GMA_DEFAULT_MMIO); + + /* Enable response in IO and MMIO space. */ + pci_or_config16(SA_DEV_IGD, PCI_COMMAND, + (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); +} diff --git a/src/soc/intel/common/block/include/intelblocks/igd_init.h b/src/soc/intel/common/block/include/intelblocks/igd_init.h new file mode 100644 index 0000000..2423c23 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/igd_init.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_GRAPHICS_IGD_INIT_H +#define SOC_INTEL_COMMON_BLOCK_GRAPHICS_IGD_INIT_H + +/* + * Enable MMIO and port IO of the Intel Graphics Device and program the Base + * Address Range 0 according to the CONFIG_GFX_GMA_DEFAULT_MMIO configuration + * element. + */ +void igd_init(void); + +#endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_IGD_INIT_H */