Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/23669
Change subject: nb/intel/haswell: Get rid off device_t ......................................................................
nb/intel/haswell: Get rid off device_t
Use of `device_t` has been abandoned in ramstage
Change-Id: Ica914a76f4638621e12441adb29731ab078d8bee Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c 4 files changed, 19 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/23669/1
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index e032948..d8ac4e2 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -25,7 +25,7 @@
unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c7319fb..3a348d2 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -487,7 +487,7 @@ intel_gma_restore_opregion(); }
-static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -501,7 +501,7 @@ const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); if (!dev) { return NULL; } @@ -509,7 +509,7 @@ return &chip->gfx; }
-static void gma_ssdt(device_t device) +static void gma_ssdt(struct device *device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 9e7ce0e..6c528da 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -103,7 +103,7 @@ } }
-static void minihd_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void minihd_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 32be916..68cc647 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -33,7 +33,7 @@ #include "chip.h" #include "haswell.h"
-static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; u32 mask; @@ -69,7 +69,7 @@ return 0; }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ .ops_pci_bus = pci_bus_default_ops, };
-static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar;
@@ -106,7 +106,7 @@ /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar;
@@ -125,7 +125,7 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -145,7 +145,7 @@ * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i;
@@ -202,7 +202,7 @@ const char *description; };
-static void read_map_entry(device_t dev, struct map_entry *entry, uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask; @@ -270,7 +270,7 @@ [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), };
-static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -278,7 +278,7 @@ } }
-static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -289,7 +289,7 @@ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); }
-static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -381,7 +381,7 @@ #endif }
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -393,7 +393,7 @@ mc_add_dram_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -457,7 +457,7 @@ .device = PCI_DEVICE_ID_HSW_ULT, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { bsp_init_and_start_aps(dev->link_list); } @@ -470,7 +470,7 @@ .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) {