HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45610 )
Change subject: src: Move DEFAULT_MCHBAR to Kconfig ......................................................................
src: Move DEFAULT_MCHBAR to Kconfig
Change-Id: Idca25b2e4bf65abcb3f8b150452ab2567baa60c3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/dell/optiplex_9010/early_init.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c A src/northbridge/intel/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/memmap.h M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/acpi/hostbridge.asl M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/memmap.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/memmap.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/acpi/x4x.asl M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/iomap.h M src/northbridge/intel/x4x/x4x.h 51 files changed, 88 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45610/1
diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 81eb6f4..b5c23bc 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -85,7 +85,7 @@
struct pei_data pd = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c index e96ee34..4947ff0 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -32,8 +32,8 @@ * FIXME: the board gets stuck in reset loop in * mainboard_romstage_entry. Avoid that by clearing SSKPD */ - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); MCHBAR16(SSKPD_HI) = 0;
sch5545_early_init(0x2e); diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 2ffa3aa..ecfdfab 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -79,7 +79,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index f3da77c..f8e8553 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -86,7 +86,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f0ffc9f..68e7905 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -54,7 +54,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index f2f21bc..8fd923f 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -91,7 +91,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 391d1f2..c83a110 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -14,7 +14,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index a2aaf33b..a44ee24 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -51,7 +51,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index d1aa9d5..85c87c1 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -56,7 +56,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index bb120bf..f08ea8c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -12,7 +12,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 5b55873..fc0eaec 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -10,7 +10,7 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 7076eb7..f43b21a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,7 +40,7 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index ad4ddb9..3c1887a 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -117,7 +117,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 7d4a9a4..03ddf21 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -101,7 +101,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig new file mode 100644 index 0000000..3c2bb66 --- /dev/null +++ b/src/northbridge/intel/Kconfig @@ -0,0 +1,4 @@ +#SPDX-License-Identifier: GPL-2.0-or-later + +config DEFAULT_MCHBAR + hex diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index f5d6712..788e15a 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -14,6 +14,10 @@ select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP
+config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e..2051afa 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -14,7 +14,7 @@ // now. Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 1be3518..25daf38 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -9,7 +9,7 @@ const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */ pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index dc993cf..fe5a265 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -171,10 +171,8 @@ (could be reduced to 10 bytes) */
#ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) #define DEFAULT_DMIBAR ((u8 *)0xfed18000) #else -#define DEFAULT_MCHBAR 0xfed14000 #define DEFAULT_DMIBAR 0xfed18000 #endif #define DEFAULT_EPBAR 0xfed19000 @@ -237,9 +235,9 @@ * MCHBAR */
-#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) *((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + x))
#define HPLLVCO_MCHBAR 0x0c0f
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 5a4999e..ffb52c8 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -268,7 +268,7 @@ /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR; + DMIBAR32(DMILE2A) = (uintptr_t)CONFIG_DEFAULT_MCHBAR; }
void gm45_late_init(const stepping_t stepping) diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 84be33d..5152645 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -9,6 +9,10 @@
if NORTHBRIDGE_INTEL_HASWELL
+config DEFAULT_MCHBAR + hex + default 0xfed10000 + config HASWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT bool "Start verstage in bootblock" diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debf..243cb25 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -13,7 +13,7 @@
Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1d4eba6..e42c356 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -88,7 +88,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */
- OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, CONFIG_DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b9c2c03 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -16,8 +16,8 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7..a1125ab 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -28,9 +28,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index ac3b1db..2c1aa6a 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -7,7 +7,6 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 5b025eb..f922e68 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -47,7 +47,7 @@
struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .mchbar = (uintptr_t)CONFIG_DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d6498f1..0499a7c 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -15,6 +15,10 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP
+config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225c..76a50f0 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -39,7 +39,7 @@
Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b04a2f594..0bdcd17 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -145,7 +145,7 @@ printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4b79b2b..96623be 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -6,10 +6,8 @@ /* Northbridge BARs */ #define DEFAULT_X60BAR 0xfed13000 #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ #else -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ @@ -99,9 +97,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x))))
/* Chipset Control Registers */ #define FSBPMC3 0x40 /* 32bit */ diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index fbad4be..4c77849 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -11,6 +11,10 @@
if NORTHBRIDGE_INTEL_IRONLAKE
+config DEFAULT_MCHBAR + hex + default 0xfed10000 + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index d6a2cf8..bdfd281 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -48,7 +48,7 @@ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */
- OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, CONFIG_DEFAULT_MCHBAR, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 3cf597d..4a09ee1 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -12,7 +12,7 @@
Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index fa89bd9..7b4c11f 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -19,7 +19,7 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 7ed6afd..20de8f5 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -26,10 +26,8 @@
/* Northbridge BARs */ #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ #else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ @@ -100,9 +98,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index a1b0894..7d2f7b1 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -15,6 +15,10 @@ select INTEL_GMA_ACPI select PARALLEL_MP
+config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VGA_BIOS_ID string default "8086,a001" diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 9515c31..1e6cf4d 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -14,7 +14,7 @@
Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..7a7cc32 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -137,7 +137,7 @@
/* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1);
diff --git a/src/northbridge/intel/pineview/memmap.h b/src/northbridge/intel/pineview/memmap.h index 50ede0b..0075cd9 100644 --- a/src/northbridge/intel/pineview/memmap.h +++ b/src/northbridge/intel/pineview/memmap.h @@ -3,7 +3,6 @@ #ifndef PINEVIEW_MEMMAP_H #define PINEVIEW_MEMMAP_H
-#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_PMIOBAR 0x00000400 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..0df17a5 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -38,9 +38,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..8ab557d 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -9,6 +9,10 @@
if NORTHBRIDGE_INTEL_SANDYBRIDGE
+config DEFAULT_MCHBAR + hex + default 0xfed10000 + config SANDYBRIDGE_VBOOT_IN_ROMSTAGE bool default n diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..92165b0 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -52,8 +52,8 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
diff --git a/src/northbridge/intel/sandybridge/memmap.h b/src/northbridge/intel/sandybridge/memmap.h index 9825125..bd40252 100644 --- a/src/northbridge/intel/sandybridge/memmap.h +++ b/src/northbridge/intel/sandybridge/memmap.h @@ -4,7 +4,6 @@ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__
/* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 697862f..b9defda 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -229,7 +229,7 @@
static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->mchbar = (uintptr_t)CONFIG_DEFAULT_MCHBAR; pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; pei_data->epbar = DEFAULT_EPBAR; pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8f9d118..fdb1795 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -49,9 +49,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8..b76c78c 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -13,6 +13,10 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP
+config DEFAULT_MCHBAR + hex + default 0xfed14000 + config CBFS_SIZE hex default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 51deea8..ee30098 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -12,7 +12,7 @@
Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d3c3308..4921774 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -16,7 +16,7 @@ void x4x_early_init(void) { /* Setup MCHBAR. */ - pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */ pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h index 22a675f..03b1b18 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/iomap.h @@ -3,7 +3,6 @@ #ifndef X4X_IOMAP_H #define X4X_IOMAP_H
-#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_HECIBAR 0xfed10000 diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 45785a0..95c79e2 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -40,9 +40,9 @@ * MCHBAR */
-#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR8_AND_OR(x, and, or) \