[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Enable Hybrid storage mode

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46420 )

Change subject: mb/intel/adlrvp: Enable Hybrid storage mode
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mb/intel/adlrvp: Enable Hybrid storage mode

TEST=Build and test booting ADL RVP form NVMe and Optane
localhost ~ # lspci -d :f1a6
Show all the NVMe devices and be really verbose
localhost ~ # lspci -vvvd :f1a6
Print PCIe lane capabilities and configurations for all the NVMe devices.

Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/46420/1

diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
index fadf602..c5103ce 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -72,6 +72,9 @@
    # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
    register "PcieClkSrcUsage[6]" = "0xff"

+	# Hybrid storage mode
+	register "HybridStorageMode" = "1"
+
    register "SataSalpSupport" = "1"

register "SataPortsEnable" = "{