Justin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79755?usp=email )
Change subject: mb/dell: Add Dell Precision M4800 (Haswell) ......................................................................
mb/dell: Add Dell Precision M4800 (Haswell)
Port of the Dell Precision M4800, a haswell workstation with an MXM type-A slot. The MXM slot works with any other MXM GPUs, including GPUs this board does not boot on vendor firmware. Libgfxinit does not appear to work, possibly due to some unusual graphics setup but a workaround is to use EDK2 and add a Gop driver to the Tianocore build. The EC is the SMSC MEC5055 which seems to be compatible with the MEC5035 code. Based on Nicholas Chin's E6430 port.
Working: - USB EHCI debug (left side usb port closest to the touchpad) - Keyboard - Touchpad/trackpoint - Ethernet - Headphone port - SD card reader - mPCIe WiFi (With the MEC5035 radio enables commit) - SeaBIOS 1.16.2 - edk2 (MrChromebox's fork, uefipayload_202309) - dGPU (NVIDIA Quadro K2100M, NVIDIA GeForce GTX 1050) - SATA DVD Drive - SATA SSD - SATA M.2 - DisplayPort - Internal flashing - Broadwell MRC - Battery reporting (acpi copied from vendor)
Not working: - S3 suspend: may be a similar issue to the E6430 - Physical Wireless switch - Battery reporting - Brightness hotkeys - Lid close suspend
Unknown/Untested: - ExpressCard - Speakers (unclear if I broke mine or they don't work) - TPM - Dock
Change-Id: I49870b28be943dcb1932909f9d3ec4207cc11436 Signed-off-by: Justin Wu jxw5883@runbox.io --- A src/mainboard/dell/precision_m4800/Kconfig A src/mainboard/dell/precision_m4800/Kconfig.name A src/mainboard/dell/precision_m4800/Makefile.inc A src/mainboard/dell/precision_m4800/acpi/ac.asl A src/mainboard/dell/precision_m4800/acpi/battery.asl A src/mainboard/dell/precision_m4800/acpi/ec.asl A src/mainboard/dell/precision_m4800/acpi/platform.asl A src/mainboard/dell/precision_m4800/acpi/superio.asl A src/mainboard/dell/precision_m4800/board_info.txt A src/mainboard/dell/precision_m4800/cmos.default A src/mainboard/dell/precision_m4800/cmos.layout A src/mainboard/dell/precision_m4800/data.vbt A src/mainboard/dell/precision_m4800/devicetree.cb A src/mainboard/dell/precision_m4800/dsdt.asl A src/mainboard/dell/precision_m4800/early_init.c A src/mainboard/dell/precision_m4800/gma-mainboard.ads A src/mainboard/dell/precision_m4800/gpio.c A src/mainboard/dell/precision_m4800/hda_verb.c A src/mainboard/dell/precision_m4800/mainboard.c A src/mainboard/dell/precision_m4800/romstage.c 20 files changed, 1,576 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/79755/1
diff --git a/src/mainboard/dell/precision_m4800/Kconfig b/src/mainboard/dell/precision_m4800/Kconfig new file mode 100644 index 0000000..53ce8e0 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/Kconfig @@ -0,0 +1,39 @@ +if BOARD_DELL_PRECISION_M4800 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM1 + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + select EC_DELL_MEC5035 + select GFX_GMA_PANEL_1_ON_EDP + +config MAINBOARD_DIR + string + default "dell/precision_m4800" + +config MAINBOARD_PART_NUMBER + string + default "Precision M4800" + +config VGA_BIOS_ID + string + default "8086,0416" + +config USBDEBUG_HCD_INDEX + int + default 2 + +endif diff --git a/src/mainboard/dell/precision_m4800/Kconfig.name b/src/mainboard/dell/precision_m4800/Kconfig.name new file mode 100644 index 0000000..5b824ed --- /dev/null +++ b/src/mainboard/dell/precision_m4800/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_DELL_PRECISION_M4800 + bool "Precision M4800" diff --git a/src/mainboard/dell/precision_m4800/Makefile.inc b/src/mainboard/dell/precision_m4800/Makefile.inc new file mode 100644 index 0000000..7a72252 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/precision_m4800/acpi/ac.asl b/src/mainboard/dell/precision_m4800/acpi/ac.asl new file mode 100644 index 0000000..8049525 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/acpi/ac.asl @@ -0,0 +1,53 @@ +Scope (_SB) +{ + Mutex (ECAX, 0x01) + Method (EEAC, 2, Serialized) + { + Acquire (ECAX, 0xFFFF) + Name (EABF, Buffer (0x08){}) + CreateDWordField (EABF, Zero, ECST) + CreateDWordField (EABF, 0x04, ECPA) + ECST = Arg0 + ECPA = Arg1 + //EABF = GENS (0x07, EABF, SizeOf (EABF)) + Local0 = ECST /* _SB_.EEAC.ECST */ + Release (ECAX) + Return (Local0) + } + Device (AC) + { + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (Package (0x04) + { + _SB, + BAT0, + BAT1, + BAT2 + }) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Local0 = ECG5 () + Local0 &= One + If ((Local0 != PWRS)) + { + PWRS = Local0 + PNOT () + } + + Return (Local0) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + } + Method (ACEV, 2, NotSerialized) + { + Notify (AC, 0x80) // Status Change + } +} diff --git a/src/mainboard/dell/precision_m4800/acpi/battery.asl b/src/mainboard/dell/precision_m4800/acpi/battery.asl new file mode 100644 index 0000000..85222e1 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/acpi/battery.asl @@ -0,0 +1,421 @@ +Scope (_SB) +{ + Mutex (ECM1, 0x01) + Method (ECRB, 1, NotSerialized) + { + Return (_SB.PCI0.LPCB.EC.ECR1 (Arg0)) + } + + Method (ECG2, 0, NotSerialized) + { + Return (ECBT (Zero, One)) + } + + Method (ECG5, 0, NotSerialized) + { + Local0 = ECRB (0x06) + Return (Local0) + } + + Method (ECRW, 1, NotSerialized) + { + Return (_SB.PCI0.LPCB.EC.ECR2 (Arg0)) + } + + Method (ECWB, 2, NotSerialized) + { + _SB.PCI0.LPCB.EC.ECW1 (Arg0, Arg1) + } + + Method (ECBT, 2, NotSerialized) + { + Local0 = _SB.PCI0.LPCB.EC.ECR1 (Arg0) + Local0 &= Arg1 + If (Local0) + { + Return (One) + } + + Return (Zero) + } + + Method (ECG6, 2, NotSerialized) + { + Acquire (ECM1, 0xFFFF) + Local2 = ECG2 () + ECWB (0x03, Arg0) + Arg1 [Zero] = ECRB (0x10) + Local0 = ECRW (0x12) + If ((Local0 == Zero)) + { + Local0++ + } + ElseIf ((Local2 != Zero)) + { + If ((Local0 & 0x8000)) + { + Local0 = Ones + } + } + ElseIf ((Local0 & 0x8000)) + { + Local0 = (Zero - Local0) + Local0 &= 0xFFFF + } + Else + { + Local0 = Ones + } + + Arg1 [One] = Local0 + Local0 = ECRW (0x16) + Arg1 [0x02] = Local0 + Local0 = ECRW (0x14) + Arg1 [0x03] = Local0 + Release (ECM1) + } + + Method (ECM8, 1, NotSerialized) + { + ECWB (0x04, Arg0) + Name (LBUF, Buffer (0x21){}) + Local0 = Zero + While ((Local0 < 0x20)) + { + Local1 = ECRB (0x2A) + LBUF [Local0] = Local1 + If ((Local1 == Zero)) + { + Break + } + + Local0++ + } + + If ((Local1 != Zero)) + { + LBUF [Local0] = Zero + Local0++ + } + + Local0++ + Name (OBUF, Buffer (Local0){}) + OBUF = LBUF /* \ECM8.LBUF */ + Return (OBUF) /* \ECM8.OBUF */ + } + + Name (BS01, Package (0x03) + { + One, + 0xFF, + "Unknown" + }) + Name (BS02, Package (0x0F) + { + 0x03, + 0x02, + "Sony", + 0x03, + "Sanyo", + 0x04, + "Panasonic", + 0x07, + "SMP", + 0x08, + "Motorola", + 0x06, + "Samsung SDI", + 0xFF, + "Unknown" + }) + Name (BS03, Package (0x13) + { + 0x02, + One, + "PbAc", + 0x02, + "LION", + 0x03, + "NiCd", + 0x04, + "NiMH", + 0x05, + "NiZn", + 0x06, + "RAM", + 0x07, + "ZnAR", + 0x08, + "LiP", + 0xFF, + "Unknown" + }) + Method (XPTB, 1, NotSerialized) + { + Local0 = SizeOf (Arg0) + If ((ObjectType (Arg0) == 0x02)) + { + Local0++ + } + + Name (OBUF, Buffer (Local0){}) + OBUF = Arg0 + If ((ObjectType (Arg0) == 0x02)) + { + Local0-- + OBUF [Local0] = Zero + } + + Return (OBUF) /* \XPTB.OBUF */ + } + Method (STDG, 3, NotSerialized) + { + Local0 = Arg0 + If ((Arg0 >= 0x0A)) + { + Divide (Arg0, 0x0A, Local0, Local1) + Arg2 = STDG (Local1, Arg1, Arg2) + } + + Local0 += 0x30 + Arg1 [Arg2] = Local0 + Arg2++ + Return (Arg2) + } + Method (XPTS, 1, NotSerialized) + { + Name (LBUF, Buffer (0x20){}) + Local0 = STDG (Arg0, LBUF, Zero) + LBUF [Local0] = Zero + Local0++ + Name (OBUF, Buffer (Local0){}) + OBUF = LBUF /* \XPTS.LBUF */ + Return (OBUF) /* \XPTS.OBUF */ + } + Method (ECU0, 2, NotSerialized) + { + Local0 = One + Local1 = Zero + While ((Local1 != 0xFF)) + { + Local1 = DerefOf (Arg0 [Local0]) + If ((Arg1 == Local1)) + { + Local0++ + Local2 = DerefOf (Arg0 [Local0]) + Local2 = XPTB (Local2) + Return (Local2) + } + + Local0 += 0x02 + } + + Local2 = DerefOf (Arg0 [Zero]) + Local2 = ECM8 (Local2) + Return (Local2) + } + Method (ECG9, 2, NotSerialized) + { + Acquire (ECM1, 0xFFFF) + ECWB (0x03, Arg0) + Arg1 [Zero] = One + Local0 = ECRW (0x20) + Arg1 [One] = Local0 + Local1 = ECRW (0x1E) + Arg1 [0x02] = Local1 + Arg1 [0x03] = One + Local2 = ECRW (0x22) + Arg1 [0x04] = Local2 + Local3 = Local0 / 0x0A + Arg1 [0x05] = Local3 + Local3 = Local0 / 0x21 + Arg1 [0x06] = Local3 + Local3 = Local0 / 0x64 + Arg1 [0x07] = Local3 + Arg1 [0x08] = Local3 + Local3 = ECU0 (BS01, Zero) + Arg1 [0x09] = Local3 + Local3 = ECRW (0x26) + Local3 = XPTS (Local3) + Arg1 [0x0A] = Local3 + Local3 = ECRB (0x29) + Local3 = ECU0 (BS03, Local3) + Arg1 [0x0B] = Local3 + Local3 = ECRB (0x28) + Local3 = ECU0 (BS02, Local3) + Arg1 [0x0C] = Local3 + Release (ECM1) + } + Device (BAT0) + { + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_PCL, Package () {_SB}) // _PCL: Power Consumer List + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = ECG5 () + Local0 &= 0x02 + If (Local0) + { + Return (0x1F) + } + + Return (0x0F) + } + + Method (_BIF, 0, Serialized) // _BIF: Battery Information + { + Name (BIF0, Package (0x0D){}) + ECG9 (One, BIF0) + Return (BIF0) /* _SB_.BAT0._BIF.BIF0 */ + } + + Method (_BST, 0, Serialized) // _BST: Battery Status + { + Name (BST0, Package (0x04){}) + ECG6 (One, BST0) + Return (BST0) /* _SB_.BAT0._BST.BST0 */ + } + } + + Device (BAT1) + { + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = EEAC (0x05, Zero) + If ((Local0 < 0x02)) + { + Return (Zero) + } + + Local0 = ECG5 () + Local0 &= 0x08 + If (Local0) + { + Return (0x1F) + } + + Return (0x0F) + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Name (BIF1, Package (0x0D){}) + ECG9 (0x02, BIF1) + Return (BIF1) /* _SB_.BAT1._BIF.BIF1 */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Name (BST1, Package (0x04){}) + ECG6 (0x02, BST1) + Return (BST1) /* _SB_.BAT1._BST.BST1 */ + } + } + + Device (BAT2) + { + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = EEAC (0x05, Zero) + If ((Local0 < 0x03)) + { + Return (Zero) + } + + Local0 = ECG5 () + Local0 &= 0x20 + If (Local0) + { + Return (0x1F) + } + + Return (Zero) + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + Name (BIF1, Package (0x0D){}) + ECG9 (0x03, BIF1) + Return (BIF1) /* _SB_.BAT2._BIF.BIF1 */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + Name (BST1, Package (0x04){}) + ECG6 (0x03, BST1) + Return (BST1) /* _SB_.BAT2._BST.BST1 */ + } + } + + Method (BTEV, 2, NotSerialized) + { + If ((Arg0 == One)) + { + If ((Arg1 == Zero)) + { + Notify (BAT0, 0x81) // Information Change + } + + If ((Arg1 == One)) + { + Notify (BAT1, 0x81) // Information Change + } + Else + { + Notify (BAT2, 0x81) // Information Change + } + } + + If ((Arg0 == 0x02)) + { + If ((Arg1 == Zero)) + { + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + } + + If ((Arg1 == One)) + { + Notify (BAT1, 0x80) // Status Change + Notify (BAT1, 0x81) // Information Change + } + Else + { + Notify (BAT2, 0x80) // Status Change + Notify (BAT2, 0x81) // Information Change + } + } + + If ((Arg0 == 0x03)) + { + If ((Arg1 == Zero)) + { + Notify (BAT0, 0x80) // Status Change + } + + If ((Arg1 == One)) + { + Notify (BAT1, 0x80) // Status Change + } + Else + { + Notify (BAT2, 0x80) // Status Change + } + } + } +} + diff --git a/src/mainboard/dell/precision_m4800/acpi/ec.asl b/src/mainboard/dell/precision_m4800/acpi/ec.asl new file mode 100644 index 0000000..dd116d7 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/acpi/ec.asl @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 16) + Mutex (ECLK, 1) + //Mutex (ECSX, 0x01) + Name (ECRD, Zero) + Name (ECRS, ResourceTemplate () + { + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x01, // Length + _Y36) + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x00, // Alignment + 0x01, // Length + _Y37) + }) + Method (_STA, 0, Serialized) // _STA: Status + { + Return (0x0F) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + CreateWordField (ECRS, _SB.PCI0.LPCB.EC._Y36._MIN, DMIN) // _MIN: Minimum Base Address + CreateWordField (ECRS, _SB.PCI0.LPCB.EC._Y36._MAX, DMAX) // _MAX: Maximum Base Address + CreateWordField (ECRS, _SB.PCI0.LPCB.EC._Y37._MIN, CMIN) // _MIN: Minimum Base Address + CreateWordField (ECRS, _SB.PCI0.LPCB.EC._Y37._MAX, CMAX) // _MAX: Maximum Base Address + Local0 = (0x0900 + 0x30) + DMIN = Local0 + DMAX = Local0 + Local0 = (0x0900 + 0x34) + CMIN = Local0 + CMAX = Local0 + Return (ECRS) /* _SB_.PCI0.LPCB.ECDV.ECRS */ + } +/* FIXME: EC support */ + OperationRegion (ERAM, EmbeddedControl, 0, 0xFF) + Field (ERAM, ByteAcc, Lock, Preserve) + { + EC00, 8, + EC01, 8, + EC02, 8, + EC03, 8, + EC04, 8, + EC05, 8, + EC06, 8, + EC07, 8, + EC08, 8, + EC09, 8, + EC10, 8, + EC11, 8, + EC12, 8, + EC13, 8, + EC14, 8, + EC15, 8, + EC16, 8, + EC17, 8, + EC18, 8, + EC19, 8, + EC20, 8, + EC21, 8, + EC22, 8, + EC23, 8, + EC24, 8, + EC25, 8, + EC26, 8, + EC27, 8, + EC28, 8, + EC29, 8, + EC30, 8, + EC31, 8, + EC32, 8, + EC33, 8, + EC34, 8, + EC35, 8, + EC36, 8, + EC37, 8, + EC38, 8, + EC39, 8, + EC40, 8, + EC41, 8, + EC42, 8, + EC43, 8, + EC44, 8, + EC45, 8, + EC46, 8, + EC47, 8, + EC48, 8, + EC49, 8 + } + Method (ECBT, 2, NotSerialized) + { + Local0 = _SB.PCI0.LPCB.EC.ECR1 (Arg0) + Local0 &= Arg1 + If (Local0) + { + Return (One) + } + + Return (Zero) + } + Method (ECG3, 0, NotSerialized) + { + Return (ECBT (Zero, 0x10)) + } + Method (ECS2, 1, NotSerialized) + { + ECWB (One, Arg0) + } + Method (ECS3, 0, NotSerialized) + { + ECWB (0x05, One) + } + Method (ECIN, 0, NotSerialized) + { + LIDS = ECG3 () + ECS3 () + ECS2 (0x40) // (ACOS) - 0x40 is LINX, 0x80 is WIN8/WIN7 + //If ((OIDE () >= One)) + //{ + // GENS (0x2D, Zero, Zero) + //} + } + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (((Arg1 == One) == (Arg0 == 0x03))) + { + ECRD = One + ECIN () + } + + If (((Arg1 == Zero) && (Arg0 == 0x03))) + { + ECRD = Zero + } + } + + Method (ECR1, 1, NotSerialized) + { + //If ((ECRD == Zero)) + //{ + // Local0 = EISC (0x80, Arg0, Zero) + // Return (Local0) + //} + + Acquire (ECLK, 0xFFFF) + Local0 = Zero + If ((Arg0 == Zero)) + { + Local0 = EC00 /* _SB_.PCI0.LPCB.ECDV.EC00 */ + } + + If ((Arg0 == One)) + { + Local0 = EC01 /* _SB_.PCI0.LPCB.ECDV.EC01 */ + } + + If ((Arg0 == 0x02)) + { + Local0 = EC02 /* _SB_.PCI0.LPCB.ECDV.EC02 */ + } + + If ((Arg0 == 0x03)) + { + Local0 = EC03 /* _SB_.PCI0.LPCB.ECDV.EC03 */ + } + + If ((Arg0 == 0x04)) + { + Local0 = EC04 /* _SB_.PCI0.LPCB.ECDV.EC04 */ + } + + If ((Arg0 == 0x05)) + { + Local0 = EC05 /* _SB_.PCI0.LPCB.ECDV.EC05 */ + } + + If ((Arg0 == 0x06)) + { + Local0 = EC06 /* _SB_.PCI0.LPCB.ECDV.EC06 */ + } + + If ((Arg0 == 0x07)) + { + Local0 = EC07 /* _SB_.PCI0.LPCB.ECDV.EC07 */ + } + + If ((Arg0 == 0x08)) + { + Local0 = EC08 /* _SB_.PCI0.LPCB.ECDV.EC08 */ + } + + If ((Arg0 == 0x09)) + { + Local0 = EC09 /* _SB_.PCI0.LPCB.ECDV.EC09 */ + } + + If ((Arg0 == 0x0A)) + { + Local0 = EC10 /* _SB_.PCI0.LPCB.ECDV.EC10 */ + } + + If ((Arg0 == 0x0B)) + { + Local0 = EC11 /* _SB_.PCI0.LPCB.ECDV.EC11 */ + } + + If ((Arg0 == 0x0C)) + { + Local0 = EC12 /* _SB_.PCI0.LPCB.ECDV.EC12 */ + } + + If ((Arg0 == 0x0D)) + { + Local0 = EC13 /* _SB_.PCI0.LPCB.ECDV.EC13 */ + } + + If ((Arg0 == 0x0E)) + { + Local0 = EC14 /* _SB_.PCI0.LPCB.ECDV.EC14 */ + } + + If ((Arg0 == 0x0F)) + { + Local0 = EC15 /* _SB_.PCI0.LPCB.ECDV.EC15 */ + } + + If ((Arg0 == 0x10)) + { + Local0 = EC16 /* _SB_.PCI0.LPCB.ECDV.EC16 */ + } + + If ((Arg0 == 0x11)) + { + Local0 = EC17 /* _SB_.PCI0.LPCB.ECDV.EC17 */ + } + + If ((Arg0 == 0x12)) + { + Local0 = EC18 /* _SB_.PCI0.LPCB.ECDV.EC18 */ + } + + If ((Arg0 == 0x13)) + { + Local0 = EC19 /* _SB_.PCI0.LPCB.ECDV.EC19 */ + } + + If ((Arg0 == 0x14)) + { + Local0 = EC20 /* _SB_.PCI0.LPCB.ECDV.EC20 */ + } + + If ((Arg0 == 0x15)) + { + Local0 = EC21 /* _SB_.PCI0.LPCB.ECDV.EC21 */ + } + + If ((Arg0 == 0x16)) + { + Local0 = EC22 /* _SB_.PCI0.LPCB.ECDV.EC22 */ + } + + If ((Arg0 == 0x17)) + { + Local0 = EC23 /* _SB_.PCI0.LPCB.ECDV.EC23 */ + } + + If ((Arg0 == 0x18)) + { + Local0 = EC24 /* _SB_.PCI0.LPCB.ECDV.EC24 */ + } + + If ((Arg0 == 0x19)) + { + Local0 = EC25 /* _SB_.PCI0.LPCB.ECDV.EC25 */ + } + + If ((Arg0 == 0x1A)) + { + Local0 = EC26 /* _SB_.PCI0.LPCB.ECDV.EC26 */ + } + + If ((Arg0 == 0x1B)) + { + Local0 = EC27 /* _SB_.PCI0.LPCB.ECDV.EC27 */ + } + + If ((Arg0 == 0x1C)) + { + Local0 = EC28 /* _SB_.PCI0.LPCB.ECDV.EC28 */ + } + + If ((Arg0 == 0x1D)) + { + Local0 = EC29 /* _SB_.PCI0.LPCB.ECDV.EC29 */ + } + + If ((Arg0 == 0x1E)) + { + Local0 = EC30 /* _SB_.PCI0.LPCB.ECDV.EC30 */ + } + + If ((Arg0 == 0x1F)) + { + Local0 = EC31 /* _SB_.PCI0.LPCB.ECDV.EC31 */ + } + + If ((Arg0 == 0x20)) + { + Local0 = EC32 /* _SB_.PCI0.LPCB.ECDV.EC32 */ + } + + If ((Arg0 == 0x21)) + { + Local0 = EC33 /* _SB_.PCI0.LPCB.ECDV.EC33 */ + } + + If ((Arg0 == 0x22)) + { + Local0 = EC34 /* _SB_.PCI0.LPCB.ECDV.EC34 */ + } + + If ((Arg0 == 0x23)) + { + Local0 = EC35 /* _SB_.PCI0.LPCB.ECDV.EC35 */ + } + + If ((Arg0 == 0x24)) + { + Local0 = EC36 /* _SB_.PCI0.LPCB.ECDV.EC36 */ + } + + If ((Arg0 == 0x25)) + { + Local0 = EC37 /* _SB_.PCI0.LPCB.ECDV.EC37 */ + } + + If ((Arg0 == 0x26)) + { + Local0 = EC38 /* _SB_.PCI0.LPCB.ECDV.EC38 */ + } + + If ((Arg0 == 0x27)) + { + Local0 = EC39 /* _SB_.PCI0.LPCB.ECDV.EC39 */ + } + + If ((Arg0 == 0x28)) + { + Local0 = EC40 /* _SB_.PCI0.LPCB.ECDV.EC40 */ + } + + If ((Arg0 == 0x29)) + { + Local0 = EC41 /* _SB_.PCI0.LPCB.ECDV.EC41 */ + } + + If ((Arg0 == 0x2A)) + { + Local0 = EC42 /* _SB_.PCI0.LPCB.ECDV.EC42 */ + } + + If ((Arg0 == 0x2B)) + { + Local0 = EC43 /* _SB_.PCI0.LPCB.ECDV.EC43 */ + } + + If ((Arg0 == 0x2C)) + { + Local0 = EC44 /* _SB_.PCI0.LPCB.ECDV.EC44 */ + } + + If ((Arg0 == 0x2D)) + { + Local0 = EC45 /* _SB_.PCI0.LPCB.ECDV.EC45 */ + } + + If ((Arg0 == 0x2E)) + { + Local0 = EC46 /* _SB_.PCI0.LPCB.ECDV.EC46 */ + } + + If ((Arg0 == 0x2F)) + { + Local0 = EC47 /* _SB_.PCI0.LPCB.ECDV.EC47 */ + } + + If ((Arg0 == 0x30)) + { + Local0 = EC48 /* _SB_.PCI0.LPCB.ECDV.EC48 */ + } + + If ((Arg0 == 0x31)) + { + Local0 = EC49 /* _SB_.PCI0.LPCB.ECDV.EC49 */ + } + + Release (ECLK) + Return (Local0) + } + + Method (ECWB, 2, NotSerialized) + { + _SB.PCI0.LPCB.EC.ECW1 (Arg0, Arg1) + } + + Method (ECW1, 2, NotSerialized) + { + + Acquire (ECLK, 0xFFFF) + If ((Arg0 == Zero)) + { + EC00 = Arg1 + } + + If ((Arg0 == One)) + { + EC01 = Arg1 + } + + If ((Arg0 == 0x02)) + { + EC02 = Arg1 + } + + If ((Arg0 == 0x03)) + { + EC03 = Arg1 + } + + If ((Arg0 == 0x04)) + { + EC04 = Arg1 + } + + If ((Arg0 == 0x05)) + { + EC05 = Arg1 + } + + If ((Arg0 == 0x06)) + { + EC06 = Arg1 + } + + If ((Arg0 == 0x07)) + { + EC07 = Arg1 + } + + If ((Arg0 == 0x08)) + { + EC08 = Arg1 + } + + If ((Arg0 == 0x09)) + { + EC09 = Arg1 + } + + If ((Arg0 == 0x0A)) + { + EC10 = Arg1 + } + + If ((Arg0 == 0x0B)) + { + EC11 = Arg1 + } + + If ((Arg0 == 0x0C)) + { + EC12 = Arg1 + } + + If ((Arg0 == 0x10)) + { + EC16 = Arg1 + } + + If ((Arg0 == 0x11)) + { + EC17 = Arg1 + } + + Release (ECLK) + Return (Zero) + } + + Method (ECR2, 1, NotSerialized) + { + Local0 = ECR1 (Arg0) + Arg0++ + Local1 = (ECR1 (Arg0) << 0x08) + Local0 += Local1 + Return (Local0) + } + #include "acpi/battery.asl" + #include "acpi/ac.asl" +} diff --git a/src/mainboard/dell/precision_m4800/acpi/platform.asl b/src/mainboard/dell/precision_m4800/acpi/platform.asl new file mode 100644 index 0000000..faff66b --- /dev/null +++ b/src/mainboard/dell/precision_m4800/acpi/platform.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/dell/precision_m4800/acpi/superio.asl b/src/mainboard/dell/precision_m4800/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/precision_m4800/board_info.txt b/src/mainboard/dell/precision_m4800/board_info.txt new file mode 100644 index 0000000..c259823 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/dell/precision_m4800/cmos.default b/src/mainboard/dell/precision_m4800/cmos.default new file mode 100644 index 0000000..c14def1 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/cmos.default @@ -0,0 +1,9 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +bluetooth=Enable +wwan=Enable +wlan=Enable +me_state=Normal \ No newline at end of file diff --git a/src/mainboard/dell/precision_m4800/cmos.layout b/src/mainboard/dell/precision_m4800/cmos.layout new file mode 100644 index 0000000..aa9b4b5 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/cmos.layout @@ -0,0 +1,70 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: EC +412 1 e 1 bluetooth +413 1 e 1 wwan +415 1 e 1 wlan + +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: northbridge +440 8 h 0 volume + +# VBOOT +448 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +14 0 Normal +14 1 Disabled + + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/dell/precision_m4800/data.vbt b/src/mainboard/dell/precision_m4800/data.vbt new file mode 100644 index 0000000..4123061 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/data.vbt Binary files differ diff --git a/src/mainboard/dell/precision_m4800/devicetree.cb b/src/mainboard/dell/precision_m4800/devicetree.cb new file mode 100644 index 0000000..34f79b6 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/devicetree.cb @@ -0,0 +1,74 @@ +chip northbridge/intel/haswell # FIXME: check ec_present, usb_xhci_on_resume, gfx + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "4" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 220, + }" + register "usb_xhci_on_resume" = "false" + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1028 0x05cc inherit + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x005c0921" + register "gen3_dec" = "0x003c07e1" + register "gen4_dec" = "0x007c0901" + register "gpe0_en_1" = "0x1090042" + register "gpe0_en_2" = "0x0" + register "gpi0_routing" = "2" + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" + # [0] HDD1, [1] ODD, [2] Dock, [3] ESATA, [4] mSATA + register "sata_port_map" = "0x1f" + device pci 14.0 on end # xHCI Controller + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 (WWAN) + device pci 1c.1 on end # PCIe Port #2 (10/100/1G LOM) + device pci 1c.2 on end # PCIe Port #3 (WLAN) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on # PCIe Port #7 (Expresscard) + smbios_slot_desc "7" "7" "ExpressCard Slot" "8" + end + device pci 1c.7 on end # PCIe Port #8 (MMI Card reader) + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/dell/mec5035 + device pnp ff.0 on end + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Mobile Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + end +end diff --git a/src/mainboard/dell/precision_m4800/dsdt.asl b/src/mainboard/dell/precision_m4800/dsdt.asl new file mode 100644 index 0000000..88a73cd --- /dev/null +++ b/src/mainboard/dell/precision_m4800/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/precision_m4800/early_init.c b/src/mainboard/dell/precision_m4800/early_init.c new file mode 100644 index 0000000..c361d6c --- /dev/null +++ b/src/mainboard/dell/precision_m4800/early_init.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <option.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, 0x1c0f); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/precision_m4800/gma-mainboard.ads b/src/mainboard/dell/precision_m4800/gma-mainboard.ads new file mode 100644 index 0000000..fd10cad --- /dev/null +++ b/src/mainboard/dell/precision_m4800/gma-mainboard.ads @@ -0,0 +1,20 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + HDMI1, + Analog, + LVDS, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/precision_m4800/gpio.c b/src/mainboard/dell/precision_m4800/gpio.c new file mode 100644 index 0000000..ac46652 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/gpio.c @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/precision_m4800/hda_verb.c b/src/mainboard/dell/precision_m4800/hda_verb.c new file mode 100644 index 0000000..2ce6e14 --- /dev/null +++ b/src/mainboard/dell/precision_m4800/hda_verb.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805cc, /* Subsystem ID */ + 32, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805cc), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, 0x02a19031), + AZALIA_PIN_CFG(0, 0x19, 0x01a1903e), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x02050020, 0x02048014, 0x02050020, 0x02040014, //1f + 0x0205001c, 0x02040800, 0x0205006d, 0x0204aa10, //20 + 0x02050076, 0x0204000e, 0x0205006c, 0x02042400, //21 + 0x0205006b, 0x0204c429, 0x02050018, 0x02047308, //22 + 0x02050025, 0x0204ebc4, 0x02050025, 0x0204ebc2, //23 + 0x02050026, 0x02044028, 0x02050029, 0x02040250, + 0x02050079, 0x02043140, 0x0205000a, 0x02040f81, + 0x0205001a, 0x02049ad2, 0x02050014, 0x02040710, + 0x02050005, 0x0204ff1f, 0x02050079, 0x02043140, + 0x02050075, 0x02040000, 0x02050075, 0x02040000, + 0x05350000, 0x0534601a, 0x05450000, 0x05442000, + 0x0535003d, 0x05340800, 0x0535003e, 0x05340800, + 0x05350003, 0x05341ef8, 0x05350016, 0x05341ee1, + 0x05350023, 0x05341f7b, 0x05350030, 0x05341fbd, + 0x05350004, 0x05340000, 0x05350004, 0x05340000, + 0x0545003d, 0x05440800, 0x0545003e, 0x05440800, + 0x05450003, 0x05441ef8, 0x05450016, 0x05441ee1, + 0x05450023, 0x05441f7b, 0x05450030, 0x05441fbd, + 0x05450004, 0x05440000, 0x05350000, 0x0534e01a, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/precision_m4800/mainboard.c b/src/mainboard/dell/precision_m4800/mainboard.c new file mode 100644 index 0000000..925dd3c --- /dev/null +++ b/src/mainboard/dell/precision_m4800/mainboard.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> +#include <ec/dell/mec5035/mec5035.h> + +static void mainboard_init(struct device *dev) +{ + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/precision_m4800/romstage.c b/src/mainboard/dell/precision_m4800/romstage.c new file mode 100644 index 0000000..c8e1fed --- /dev/null +++ b/src/mainboard/dell/precision_m4800/romstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + /* FIXME: check this */ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};