Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48466 )
Change subject: drivers/intel/fsp2_0: Use coreboot postcar with FSP-T ......................................................................
drivers/intel/fsp2_0: Use coreboot postcar with FSP-T
Allow platforms to use the coreboot postcar code instead of calling into FSP-M TempRamExit API.
There are several reasons to do this: - Tearing down CAR is easy. - Allows having control over MTRR's and caching in general. - The MTRR's set up in postcar be it by coreboot or FSP-M are overwritten later on during CPU init so it does not matter. - Avoids having to find a CBFS file before cbmem is up (this causes problems with cbfs_mcache)
Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466 Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/soc/intel/common/block/cpu/Makefile.inc 3 files changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 056c35c..551b4b9 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -126,6 +126,13 @@ defined in the FSP specification but in the SOC integration guides.
+config NO_FSP_TEMP_RAM_EXIT + bool + depends on FSP_CAR + help + Select this on a platform where you want to use FSP-T but use + coreboot code to tear down CAR. + config FSP_M_XIP bool default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 25e2846..b518bec 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -29,7 +29,9 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma_core.c
+ifneq ($(CONFIG_NO_FSP_TEMP_RAM_EXIT),y) postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c +endif postcar-$(CONFIG_FSP_CAR) += util.c postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c postcar-y += hand_off_block.c diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 7692076..5131658 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,6 +1,10 @@ ifeq ($(CONFIG_FSP_CAR),y) bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU)+= car/cache_as_ram_fsp.S +ifeq ($(CONFIG_NO_FSP_TEMP_RAM_EXIT),y) +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += car/exit_car.S +else postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += car/exit_car_fsp.S +endif else bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S