Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 )
Change subject: soc/intel/jasperlake: Move reserved gpio at the end of comm pad group ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46842/2/src/soc/intel/jasperlake/gp... File src/soc/intel/jasperlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/46842/2/src/soc/intel/jasperlake/gp... PS2, Line 50: INTEL_GPP(GPP_H0, GPIO_RSVD_12, GPIO_RSVD_13),
Ack
Thanks for sharing more context. It helps.
https://review.coreboot.org/c/coreboot/+/46842/4/src/soc/intel/jasperlake/gp... File src/soc/intel/jasperlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/46842/4/src/soc/intel/jasperlake/gp... PS4, Line 37: INTEL_GPP_BASE(GPP_F0, GPP_B0, GPP_B23, 32), /* GPP_B */ : INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_RSVD_11, 64), /* GPP_A */ : INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96), /* GPP_S */ : INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128), /* GPP_R */ HOSTSW_OWN register for GPP_B is at offset 0xC8, GPP_A at 0xCC, GPP_S at 0xD0, GPP_R at 0xD4.
This update will mess up with those GPIO groups.
https://review.coreboot.org/c/coreboot/+/46842/4/src/soc/intel/jasperlake/gp... PS4, Line 60: INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288) Going by your explanation, this group's HOSTSW_OWN register will be at offset 0xC0. But the EDS says that the HOSTSW_OWN register for GPP_E group is at offset 0xC4.