Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56004 )
Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen ......................................................................
soc/intel/common/block/acpi: Move pep.asl to acpigen
There is a use-case for generating the AML bytecode at runtime for the Intel Power Engine device, which comes in a followup patch.
BUG=b:185437326 TEST=select this on brya, dump SSDT: Scope (_SB.PCI0) { Device (PEPD) { Name (_HID, "INT33A1") Name (_CID, EisaId ("INT33A1") Method (_DSM, 4, Serialized) { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x63 }) } If ((Local1 == One)) { Return (Package (0x01) { Package (0x03) { \NULL, Zero, Package (0x02) { Zero, Package (0x02) { 0xFF, Zero } } } }) } If ((Local1 == 0x02)){} If ((Local1 == 0x03)){} If ((Local1 == 0x04)){} If ((Local1 == 0x05)) { If (CondRefOf (_SB.PCI0.LPCB.EC0.S0IX)) { _SB.PCI0.LPCB.EC0.S0IX (One) }
If (CondRefOf (_SB.MS0X)) { _SB.MS0X (One) }
If (CondRefOf (_SB.PCI0.EGPM)) { _SB.PCI0.EGPM () } }
If ((Local1 == 0x06)) { If (CondRefOf (_SB.PCI0.LPCB.EC0.S0IX)) { _SB.PCI0.LPCB.EC0.S0IX (Zero) }
If (CondRefOf (_SB.MS0X)) { _SB.MS0X (Zero) }
If (CondRefOf (_SB.PCI0.RGPM)) { _SB.PCI0.RGPM () } }
Return (Buffer (One) { 0x00 }) }
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/Makefile.inc A src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 140 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/56004/1
diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 6aa3abc..12c0d45 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -15,6 +15,12 @@ help Generate LPIT table with LPI state entries
+config SOC_INTEL_COMMON_BLOCK_ACPI_PEP + bool + help + Generate an Intel Power Engine device object in the SSDT. This is + usually used for providing ACPI hooks for S0ix exit/entry. + config SOC_INTEL_COMMON_BLOCK_CRASHLOG bool depends on SOC_INTEL_CRASHLOG @@ -28,5 +34,4 @@ help Generate CPPC entries for Intel SpeedShift
- endif diff --git a/src/soc/intel/common/block/acpi/Makefile.inc b/src/soc/intel/common/block/acpi/Makefile.inc index c78dbc0..c8eaad5 100644 --- a/src/soc/intel/common/block/acpi/Makefile.inc +++ b/src/soc/intel/common/block/acpi/Makefile.inc @@ -3,3 +3,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT) += lpit.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP) += pep.c diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c new file mode 100644 index 0000000..9723d28 --- /dev/null +++ b/src/soc/intel/common/block/acpi/pep.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <intelblocks/acpi.h> +#include <soc/pci_devs.h> +#include <stdlib.h> +#include <types.h> + +#define LPI_S0_HELPER_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" +#define SYSTEM_POWER_MANAGEMENT_HID "INT33A1" +#define SYSTEM_POWER_MANAGEMENT_CID "PNP0D80" +#define EC_S0IX_HOOK "\_SB.PCI0.LPCB.EC0.S0IX" +#define MAINBOARD_HOOK "\_SB.MS0X" +#define ENABLE_PM_BITS_HOOK "\_SB.PCI0.EGPM" +#define RESTORE_PM_BITS_HOOK "\_SB.PCI0.RGPM" + +/* + * Supported functions bitmask + * bit 0: other functions than 0 are supported + * bits 1-6: function x supported + */ +static void lpi_enum_functions(void *unused) +{ + acpigen_write_return_singleton_buffer(0x63); +} + +/* + * For now there is only one disabled non-existent device, because Windows + * expects at least one device and crashes without it with a bluescreen + * (`INTERNAL_POWER_ERROR`). Returning an empty package does not work. + */ + static void lpi_get_constraints(void *unused) +{ + /* Return (Package() { Package() { "\NULL", 0, + Package() { 0, Package() { 0xff, 0 }}}}) */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(1); + acpigen_write_package(3); + acpigen_emit_namestring("\NULL"); /* non-existent */ + acpigen_write_integer(0); /* disabled, no constraints */ + acpigen_write_package(2); + acpigen_write_integer(0); /* revision */ + acpigen_write_package(2); + acpigen_write_integer(0xff); /* apply to all LPIT states */ + acpigen_write_integer(0); /* minimum D-state */ + acpigen_write_package_end(); /* inner 3 */ + acpigen_write_package_end(); /* inner 2 */ + acpigen_write_package_end(); /* inner 1 */ + acpigen_write_package_end(); /* outer */ +} + +static void lpi_empty(void *unused) +{ +} + +static void lpi_s0ix_entry(void *unused) +{ + /* Inform the EC */ + acpigen_write_if_cond_refof(EC_S0IX_HOOK); + acpigen_emit_namestring(EC_S0IX_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); + + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_refof(MAINBOARD_HOOK); + acpigen_emit_namestring(MAINBOARD_HOOK); + acpigen_write_integer(1); + acpigen_write_if_end(); + + /* Save the current PM bits then enable GPIO PM with + MISCCFG_GPIO_PM_CONFIG_BITS */ + acpigen_write_if_cond_refof(ENABLE_PM_BITS_HOOK); + acpigen_emit_namestring(ENABLE_PM_BITS_HOOK); + acpigen_write_if_end(); +} + +static void lpi_s0ix_exit(void *unused) +{ + /* Inform the EC */ + acpigen_write_if_cond_refof(EC_S0IX_HOOK); + acpigen_emit_namestring(EC_S0IX_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); + + /* Provide a board level S0ix hook */ + acpigen_write_if_cond_refof(MAINBOARD_HOOK); + acpigen_emit_namestring(MAINBOARD_HOOK); + acpigen_write_integer(0); + acpigen_write_if_end(); + + /* Restore GPIO all Community PM */ + acpigen_write_if_cond_refof(RESTORE_PM_BITS_HOOK); + acpigen_emit_namestring(RESTORE_PM_BITS_HOOK); + acpigen_write_if_end(); +} + +static void (*lpi_s0_helpers[])(void *) = { + lpi_enum_functions, /* enumerate functions */ + lpi_get_constraints, /* get device constraints */ + lpi_empty, /* get crash dump device */ + lpi_empty, /* display off notify */ + lpi_empty, /* display on notify */ + lpi_s0ix_entry, /* s0ix entry */ + lpi_s0ix_exit, /* s0ix exit */ +}; + +void generate_acpi_power_engine(const struct device *dev) +{ + struct dsm_uuid ids[] = { + DSM_UUID(LPI_S0_HELPER_UUID, lpi_s0_helpers, ARRAY_SIZE(lpi_s0_helpers), NULL), + }; + + const char *scope = acpi_device_scope(dev); + + acpigen_write_scope(scope); + acpigen_write_device("PEPD"); + + acpigen_write_name_string("_HID", SYSTEM_POWER_MANAGEMENT_HID); + acpigen_write_name("_CID"); + acpigen_emit_eisaid(SYSTEM_POWER_MANAGEMENT_HID); + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); + + acpigen_write_device_end(); + acpigen_write_scope_end(); + + printk(BIOS_INFO, "%s: Intel Power Engine Plug-in\n", + acpi_device_path_join(dev->bus->dev, "PEPD")); +} diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 90d5e5e..6bba812 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -90,4 +90,7 @@ */ const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries);
+/* Generate an Intel Power Engine ACPI device */ +void generate_acpi_power_engine(const struct device *dev); + #endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */