Robbie Zhang (robbie.zhang@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18361
-gerrit
commit 301de0d96d16a759ef5470e6a789d4f920187058 Author: Robbie Zhang robbie.zhang@intel.com Date: Mon Feb 13 12:07:53 2017 -0800
soc/intel/skylake: add PrmrrSize to chip config
Prmrr configuration is supported by Kabylake FSP-M with UPD provided. It is required as one of the SGX initialization steps in BIOS.
BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set size and boot.
Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3 Signed-off-by: Robbie Zhang robbie.zhang@intel.com --- src/soc/intel/skylake/chip.h | 8 ++++++++ src/soc/intel/skylake/romstage/romstage_fsp20.c | 1 + 2 files changed, 9 insertions(+)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1b69952..07cb8b1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -376,6 +376,14 @@ struct soc_intel_skylake_config { /* Enable/Disable VMX feature */ u8 VmxEnable;
+ /* + * PRMRR size setting with three options + * 0x02000000 - 32MiB + * 0x04000000 - 64MiB + * 0x08000000 - 128MiB + */ + u32 PrmrrSize; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index e478890..a4bb684 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -139,6 +139,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) m_cfg->RMT = config->Rmt; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = config->VmxEnable; + m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i);