Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )
Change subject: soc/intel/tigerlake: Add support to initialize Memory ......................................................................
Patch Set 19:
(15 comments)
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 307: if ((info->topology == MEMORY_DOWN) || (info->topology == MIXED)) {
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Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 312: if
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Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 310: : : if
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https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 318: if
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https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 318: if
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Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 321: return
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Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 324: || (info->topology == MIXED)
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Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 328: if
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Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 349: = { : .addr_map[0] = info->smbus_info[0].addr_dimm0, : .addr_map[1] = info->smbus_info[0].addr_dimm1, : .addr_map[2] = info->smbus_info[1].addr_dimm0, : .addr_map[3] = info->smbus_info[1].addr_dimm1, : };
Ack
Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 361: if
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Making it if ((info->topology == SODIMM) || (info->topology == MIXED)) and include Mixed SPD Data len check as mentioned by Furquan below.
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 373: DDR4x
Just DDR4.
Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 377: for dq pair
for *every* dq pair
Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 389: DDR4x
Just DDR4
Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 403: unsigned int i
Ack
Done
https://review.coreboot.org/c/coreboot/+/39847/15/src/soc/intel/tigerlake/me... PS15, Line 405: init_dq_upds(mem_cfg, 4i+b, board_cfg->dq_map[i][b], : board_cfg->dq_map[i][b+1]); : init_dqs_upds(mem_cfg, 4i+b, board_cfg->dqs_map[i][b], : board_cfg->dqs_map[i][b+1]);
Ack
Done