Attention is currently required from: Paul Menzel, Angel Pons, Kyösti Mälkki, Felix Held.
Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74363 )
Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 ......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c:
https://review.coreboot.org/c/coreboot/+/74363/comment/d103d522_77949787 PS5, Line 25: const pnp_devfn_t ec_rtct_dev = PNP_DEV(0x4E, IT8528E_RTCT);
Devicetree says 0x2e for the config space?
Thank you, good catch! Checked this out, this base address is the default for the SuperIO, so the only part of this that is working is opening the LPC I/O range. I could either remove the init and assume it is at POR default or fix it to 0x2e.
I suppose it would matter if rebooting from a firmware build that had configured it differently. But even the AMI firmware uses the default address so this is probably unlikely.
What is the typical strategy for things like this? Assume it's at POR defaults or configure it explicitly?