[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add configurable value for UsbTcPortEn

[Maulik V Vaghela (Code Review)]

Attention is currently required from: Jamie Ryu, Maulik V Vaghela, Selma Bensaid, Tim Wawrzynczak, Ronak Kanabar, Patrick Rudolph.
Maulik V Vaghela has uploaded a new patch set (#6) to the change originally created by Sridhar Siricilla. ( https://review.coreboot.org/c/coreboot/+/54334 )

Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn
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soc/intel/alderlake: Add configurable value for UsbTcPortEn

As a requirement of TCSS this setting needs to be correctly set
to determine what Type-C ports are enabled on the platform.

BUG=b:184324979
TEST=Verified on brya

Signed-off-by: Sridhar Siricilla 
Change-Id: Ic5cd0690945b9296c105ade2d99f68bbf0ee22bd
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/54334/6