22 Aug
2019
22 Aug
'19
6:41 a.m.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34897 )
Change subject: arch/x86: Simplified postcar WB MTRR setup ......................................................................
Patch Set 1:
Would this approach, if applied to all intel platforms, have some issues? Do we need UC holes between cbmem_top() and TSEG?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I8822c4dcdced872a19ac183b993e8885aadd0a2c
Gerrit-Change-Number: 34897
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Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
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