Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63985 )
Change subject: northbridge/amd: Simplify fx_devs usage ......................................................................
northbridge/amd: Simplify fx_devs usage
Only single-node plaforms are actually supported, so arrays of fx_devs will always contain just one element. Remove the arrays.
TEST=Boot PC Engines apu1 (F14h) and apu2 (00730F01) into operating system. F15tn and F16kb remain untested.
Signed-off-by: Michał Kopeć michal.kopec@3mdeb.com Change-Id: I7e4385835769d4d90520e3d645ba853ef0d12803 --- M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 4 files changed, 110 insertions(+), 173 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63985/1
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e4cd187..f4131d8 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -18,12 +18,10 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <sb_cimx.h>
-#define FX_DEVS 1 - -static struct device *__f0_dev[FX_DEVS]; -static struct device *__f1_dev[FX_DEVS]; -static struct device *__f2_dev[FX_DEVS]; -static struct device *__f4_dev[FX_DEVS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0;
static u32 get_io_addr_index(u32 nodeid, u32 linkn) @@ -44,10 +42,10 @@ /* io range allocation */ tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); //limit - pci_write_config32(__f1_dev[0], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg);
tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev[0], reg, tempreg); + pci_write_config32(__f1_dev, reg, tempreg); }
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, @@ -57,50 +55,41 @@ u32 tempreg; /* io range allocation */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(__f1_dev[0], reg + 4, tempreg); + pci_write_config32(__f1_dev, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(__f1_dev[0], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); + pci_write_config32(__f1_dev, reg, tempreg); }
static void get_fx_devs(void) { - int i; - for (i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i + 1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } + + fx_devs = 1; }
static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); + return pci_read_config32(__f1_dev, reg); }
static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } }
@@ -134,7 +123,7 @@ res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { struct device *dev; - dev = __f0_dev[nodeid]; + dev = __f0_dev; if (!dev) continue; for (link = 0; !res && (link < 8); link++) { @@ -285,8 +274,8 @@ u64 basek, limitk; u32 hole;
- if (get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) { - hole = pci_read_config32(__f1_dev[0], 0xf0); + if (get_dram_base_limit(__f1_dev, 0, &basek, &limitk)) { + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = 0; // record the node No with hole @@ -444,20 +433,13 @@ limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base & 0x30); - } else { // io - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } + unsigned int reg_link; reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { + if (__f0_dev) { /* Reserve the resource */ struct resource *res; res = - new_resource(reg_dev, + new_resource(__f0_dev, IOINDEX(0x1000 + reg, reg_link)); if (res) { @@ -524,7 +506,7 @@ idx = 0x10; u64 basek, limitk, sizek; // 4 1T
- if (get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) { + if (get_dram_base_limit(__f1_dev, 0, &basek, &limitk)) { sizek = limitk - basek;
printk(BIOS_DEBUG, "adsr: basek = %llx, limitk = %llx, sizek = %llx.\n", diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2d7e93b..59e141b 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -22,83 +22,65 @@ #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h>
-#define MAX_NODE_NUMS MAX_NODES - static unsigned int node_nums; static unsigned int sblink; -static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0;
static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); + pci_write_config32(__f1_dev, reg, tempreg); }
-static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); + pci_write_config32(__f1_dev, reg, tempreg); }
static void get_fx_devs(void) { - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + + fx_devs = 1; }
static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); + return pci_read_config32(__f1_dev, reg); }
static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } }
@@ -135,7 +117,7 @@ res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { struct device *dev; - dev = __f0_dev[nodeid]; + dev = __f0_dev; if (!dev) continue; for (link = 0; !res && (link < 8); link++) { @@ -308,7 +290,7 @@ set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8);// [39:8] } resource->flags |= IORESOURCE_STORED; snprintf(buf, sizeof(buf), " <node %x link %x>", @@ -564,7 +546,7 @@ nodeid = (limit & 0xf) + ((base>>4)&0x30); } reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; + reg_dev = __f0_dev; if (reg_dev) { /* Reserve the resource */ struct resource *res; @@ -595,9 +577,9 @@ for (i = 0; i < node_nums; i++) { u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole @@ -612,7 +594,7 @@ resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { u64 base_k, limit_k; - if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) + if (!get_dram_base_limit(__f1_dev, i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -677,7 +659,7 @@ for (i = 0; i < node_nums; i++) { u64 basek, limitk, sizek; // 4 1T
- if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node
sizek = limitk - basek; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index e754f99..3d7b343 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -26,79 +26,63 @@
static unsigned int node_nums; static unsigned int sblink; -static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0;
static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); + pci_write_config32(__f1_dev, reg, tempreg); }
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) { - u32 i; u32 tempreg; /* io range allocation */ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); + pci_write_config32(__f1_dev, reg+4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); + pci_write_config32(__f1_dev, reg, tempreg); }
static void get_fx_devs(void) { - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); + + fx_devs = 1; }
static u32 f1_read_config32(unsigned int reg) { if (fx_devs == 0) get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); + return pci_read_config32(__f1_dev, reg); }
static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } }
@@ -135,7 +119,7 @@ res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { struct device *dev; - dev = __f0_dev[nodeid]; + dev = __f0_dev; if (!dev) continue; for (link = 0; !res && (link < 8); link++) { @@ -582,7 +566,7 @@ nodeid = (limit & 0xf) + ((base>>4)&0x30); } reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; + reg_dev = __f0_dev; if (reg_dev) { /* Reserve the resource */ struct resource *res; @@ -613,9 +597,9 @@ for (i = 0; i < node_nums; i++) { u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = i; // record the node No with hole @@ -630,7 +614,7 @@ resource_t limitk_pri = 0; for (i = 0; i < node_nums; i++) { u64 base_k, limit_k; - if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) + if (!get_dram_base_limit(__f1_dev, i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -695,7 +679,7 @@ for (i = 0; i < node_nums; i++) { resource_t basek, limitk, sizek; // 4 1T
- if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node
sizek = limitk - basek; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 6bc313d..f90a64e 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -25,21 +25,15 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <southbridge/amd/pi/hudson/pci_devs.h>
-#define MAX_NODE_NUMS MAX_NODES #define PCIE_CAP_AER BIT(5) #define PCIE_CAP_ACS BIT(6)
-static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; +static struct device *__f0_dev; +static struct device *__f1_dev; +static struct device *__f2_dev; +static struct device *__f4_dev; static unsigned int fx_devs = 0;
-static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); -} - static struct device *get_mc_dev(void) { return pcidev_on_root(DEV_CDB, 0); @@ -59,32 +53,27 @@
static void get_fx_devs(void) { - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + if (fx_devs) + return; + + __f0_dev = pcidev_on_root(DEV_CDB, 0); + __f1_dev = pcidev_on_root(DEV_CDB, 1); + __f2_dev = pcidev_on_root(DEV_CDB, 2); + __f4_dev = pcidev_on_root(DEV_CDB, 4); + + if (__f1_dev == NULL || __f0_dev == NULL) { die("Cannot find 0:0x18.[0|1]\n"); } - printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); + + fx_devs = 1; }
static void f1_write_config32(unsigned int reg, u32 value) { - int i; if (fx_devs == 0) get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + if (__f1_dev && __f1_dev->enabled) { + pci_write_config32(__f1_dev, reg, value); } }
@@ -120,10 +109,10 @@ get_fx_devs();
/* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ - if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { + if (pci_read_config32(__f2_dev, 0x118) & (1 << 18)) { /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ u64 basek, limitk; - if (!get_dram_base_limit(__f1_dev[0], 0, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, 0, &basek, &limitk)) return; mmio_resource(dev, index++, limitk, 16*1024); } @@ -718,9 +707,9 @@ for (i = 0; i < get_node_nums(); i++) { u64 basek, limitk; u32 hole; - if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); + hole = pci_read_config32(__f1_dev, 0xf0); if (hole & 2) { // we find the hole mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.node_id = i; // record the node No with hole @@ -735,7 +724,7 @@ resource_t limitk_pri = 0; for (i = 0; i < get_node_nums(); i++) { u64 base_k, limit_k; - if (!get_dram_base_limit(__f1_dev[i], i, &base_k, &limit_k)) + if (!get_dram_base_limit(__f1_dev, i, &base_k, &limit_k)) continue; // no memory on this node if (base_k > 4 *1024 * 1024) break; // don't need to go to check if (limitk_pri != base_k) { // we find the hole @@ -785,7 +774,7 @@ for (i = 0; i < get_node_nums(); i++) { u64 basek, limitk, sizek; // 4 1T
- if (!get_dram_base_limit(__f1_dev[i], i, &basek, &limitk)) + if (!get_dram_base_limit(__f1_dev, i, &basek, &limitk)) continue; // no memory on this node
sizek = limitk - basek;