[coreboot-gerrit] Change in coreboot[master]: soc/intel/cmn/fast-spi: Add flash as reserved region

[Arthur Heymans (Code Review)]

Attention is currently required from: Nico Huber, Subrata Banik, Paul Menzel, Werner Zeh.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64077 )

Change subject: soc/intel/cmn/fast-spi: Add flash as reserved region
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Patch Set 2:

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi.c:

https://review.coreboot.org/c/coreboot/+/64077/comment/d634bcf5_7bac5138 
PS2, Line 528: mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, CONFIG_ROM_SIZE / KiB);
> At least on APL I know that there could be a 8MB flash chip. I find it more meaningful if we just report the used size but do not insist.

The question here is: if you have an 8M flash, can you put a PCI bar below that or not? If not because the hardware is hardcoded to decode flash there then you want to report 16M, if you can put a PCI bar then only the memory mapped portion needs to be there (so not the full flash size anyway). The safest option is just to always reserve 16M.