[coreboot-gerrit] Change in coreboot[master]: mb/intel/tglrvp: Enable Hybride storage mode

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39233 )

Change subject: mb/intel/tglrvp: Enable Hybride storage mode
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mb/intel/tglrvp: Enable Hybride storage mode

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check Pcie lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39233/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index d4b5a39..0a1e6f6 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -37,6 +37,9 @@
    register "PcieRpEnable[8]" = "1"
    register "PcieRpEnable[10]" = "1"

+	# Hybride storage mode
+	register "HybridStorageMode" = "1"
+
    register "PcieClkSrcClkReq[1]" = "1"
    register "PcieClkSrcClkReq[2]" = "2"
    register "PcieClkSrcClkReq[3]" = "3"