PraveenX Hodagatta Pranesh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36451 )
Change subject: mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36451/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36451/1//COMMIT_MSG@12 PS1, Line 12: verified MRC is restored on warm, cold, : resume boot path's
Lockdown can affect everything. Especially in the presence of undocumented […]
Nico is right. without this change MRC cache not able to update and restore on second boot due to following error "SPI Transaction Error at Flash Offset 9e0000 HSFSTS".
https://review.coreboot.org/c/coreboot/+/36451/1/src/mainboard/intel/saddleb... File src/mainboard/intel/saddlebrook/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36451/1/src/mainboard/intel/saddleb... PS1, Line 66: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
Please, add a tab.
Done