[coreboot-gerrit] [XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add header files and romstage code

[Johnny Lin (Code Review)]

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, TimLiu-SMCI, Paul Menzel, Christian Walter, Angel Pons, Jian-Ming Wang, Arthur Heymans, Srinidhi N Kaushik, Shelly Chang, Elyes Haouas, Tim Chu.

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72442 )

Change subject: soc/intel/xeon_sp/spr: Add header files and romstage code
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Patch Set 9:

(8 comments)

File src/soc/intel/xeon_sp/spr/ddr.c:

https://review.coreboot.org/c/coreboot/+/72442/comment/a7c7450f_af6c0ac4 
PS3, Line 5: get_ddr_voltage
> Please add the unit to the function name.

Done

https://review.coreboot.org/c/coreboot/+/72442/comment/29ee950f_934274a0 
PS3, Line 5: uint8_t
> Ditto.

Done

https://review.coreboot.org/c/coreboot/+/72442/comment/d81871a8_1f202947 
PS3, Line 5: uint32_t
> Please do not fix the size [1]. […]

If I understand correctly, we should use 'unsigned int' right? So I change both:
uint16_t get_max_memory_speed(uint32_t commonTck)
to
unsigned int get_ddr_millivolt(unsigned int ddr_voltage)

uint16_t get_max_memory_speed(uint32_t commonTck)
to
unsigned int get_max_memory_speed(unsigned int commonTck)

https://review.coreboot.org/c/coreboot/+/72442/comment/5410eee0_c338aa43 
PS3, Line 17: uint32_t
> Ditto.

Done

https://review.coreboot.org/c/coreboot/+/72442/comment/5e80c339_77e04b81 
PS3, Line 17: uint16_t
> Ditto.

Done

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/72442/comment/cf83017a_51c8fc2e 
PS2, Line 115: 			mupd->FspmConfig.DFXEnable = 0;
> Maybe: […]

Done

https://review.coreboot.org/c/coreboot/+/72442/comment/5e069e07_9108fe05 
PS2, Line 122: 	int port, socket;
> Could be unsigned int?

Done

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/72442/comment/f87d2e2a_023bc2ee 
PS8, Line 164: X2apic
> m_cfg->X2apic = config->x2apic; […]

Done