Attention is currently required from: Alicja Michalska, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email )
Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ......................................................................
Patch Set 8:
(7 comments)
File src/mainboard/erying/tgl/Kconfig:
https://review.coreboot.org/c/coreboot/+/80853/comment/0f8e964a_d5dddbdd : PS8, Line 24: default "erying-tgl"
"INTEL HM570". […]
Hmmm, I would use `Polestar G613 Pro` then
File src/mainboard/erying/tgl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80853/comment/4a39aefb_9909bda6 : PS8, Line 25: register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
I'm not sure if ASPM works properly when CLKREQ# isn't set up. […]
It should be fine.
File src/mainboard/erying/tgl/ramstage.c:
https://review.coreboot.org/c/coreboot/+/80853/comment/0a766542_55ed655f : PS8, Line 23: params->CpuPcieRpPeerToPeerMode[0] = 1;
AFAIK, that's needed for PCI-E Resizable BAR (ReBAR), which is pretty much mandatory for modern GPUs […]
The only boards that set this are `msi/ms7d25` and `msi/ms7e06`, with no explanation as to why
https://review.coreboot.org/c/coreboot/+/80853/comment/f9d3d0c7_6b3aeacb : PS8, Line 27: params->CpuPcieRpTransmitterHalfSwing[0] = 0;
It was configured the same way in vendor's firmware. […]
Interesting
https://review.coreboot.org/c/coreboot/+/80853/comment/f5e67070_8674bc49 : PS8, Line 41: params->PchDmiAspmCtrl = 0;
Yes. If I enable DMI ASPM, M.2 slot connected through the chipset goes haywire. […]
Whew, that's bad. I'm starting to suspect that high-speed I/O on this board is simply not well designed.
https://review.coreboot.org/c/coreboot/+/80853/comment/87ea8175_42d04d56 : PS8, Line 68: : params->CpuPcieRpFunctionSwap = 1; : params->PcieRpFunctionSwap = 0;
It was configured the same way in vendor's firmware.
It shouldn't matter, though. coreboot can handle function swapping.
https://review.coreboot.org/c/coreboot/+/80853/comment/69b029ba_95b0d40a : PS8, Line 18: : // PEG0 - Gen4 NVME : params->CpuPcieRpSlotImplemented[0] = 1; : params->CpuPcieRpAdvancedErrorReporting[0] = 1; : params->CpuPcieRpMaxPayload[0] = 2; : params->CpuPcieRpPeerToPeerMode[0] = 1; : params->CpuPcieRpPtmEnabled[0] = 1; : params->CpuPcieRpLtrEnable[0] = 1; : params->CpuPcieRpPmSci[0] = 1; : params->CpuPcieRpTransmitterHalfSwing[0] = 0; : : // PEG1 - PCI-E x16 : params->CpuPcieRpSlotImplemented[1] = 1; : params->CpuPcieRpAdvancedErrorReporting[1] = 1; : params->CpuPcieRpMaxPayload[1] = 2; : params->CpuPcieRpPeerToPeerMode[1] = 1; : params->CpuPcieRpPtmEnabled[1] = 1; : params->CpuPcieRpLtrEnable[1] = 1; : params->CpuPcieRpPmSci[1] = 1; : params->CpuPcieRpTransmitterHalfSwing[1] = 0; : : // Power management - ASPM is broken even on vendor FW : params->PchLegacyIoLowLatency = 1; : params->PchDmiAspmCtrl = 0; : : // PCH RootPorts : params->PcieRpMaxPayload[4] = 2; // M.2 Gen3 : params->PcieRpPmSci[4] = 1; : // params->PcieRpEnableCpm[4] = 0; : // params->PcieRpL1Substates[4] = 0; : // params->PcieRpAspm[4] = 0; : : params->PcieRpMaxPayload[8] = 1; : params->PcieRpPmSci[8] = 1;// M.2 NGFF : // params->PcieRpEnableCpm[8] = 0; : // params->PcieRpL1Substates[8] = 0; : // params->PcieRpAspm[8] = 0; : : params->PcieRpMaxPayload[10] = 1; // RTL8111 NIC : params->PcieRpPmSci[10] = 1; : // params->PcieRpEnableCpm[10] = 0; : // params->PcieRpL1Substates[10] = 0; : // params->PcieRpAspm[10] = 0; : : params->PcieRpMaxPayload[11] = 1; // PCI-E x1 Gen3 : params->PcieRpPmSci[11] = 1; : // params->PcieRpEnableCpm[11] = 0; : // params->PcieRpL1Substates[11] = 0; : // params->PcieRpAspm[11] = 0; : : // FSP settings : params->CpuPcieRpFunctionSwap = 1; : params->PcieRpFunctionSwap = 0; : params->ITbtPcieTunnelingForUsb4 = 0; : params->PchUsbOverCurrentEnable = 0; : params->RC1pFreqEnable = 1; : params->PavpEnable = 1; : params->CdynmaxClampEnable = 0; : params->PchEspiHostC10ReportEnable = 1;
I know, I wanted to keep devicetree as "clean" as possible, so people who aren't very familiar with […]
I'm confused because most boards I've seen don't need to configure so many FSP settings. As for devicetree settings, if they exist then please use them.