1 Sep
2020
1 Sep
'20
9:55 p.m.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45012 )
Change subject: soc/intel/common: Add SMRR Lock Supported bit definition for MTRR_CAP ......................................................................
Patch Set 3: Code-Review+2
unfortunate full circle. agreed - let's clean up the headers as a separate effort.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1254fb40c790f2a83dd11c2aabcf9bdf922b9395
Gerrit-Change-Number: 45012
Gerrit-PatchSet: 3
Gerrit-Owner: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: Caveh Jalali caveh@chromium.org
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
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Gerrit-Comment-Date: Wed, 02 Sep 2020 00:55:11 +0000
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