EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch...
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch...
PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
I kept this for special assigning : […]
@Furquan, Does PEG port have CLKREQ or just need the src? If it just need src, I think I can separate the init function or add if (type != CPU_PCIE_RP) to guard PcieClkSrcClkReq.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/48340
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
Gerrit-PatchSet: 15
Gerrit-Owner: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Meera Ravindranath
meera.ravindranath@intel.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Subrata Banik
subrata.banik@intel.com
Gerrit-Reviewer: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Wed, 09 Dec 2020 15:41:54 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Furquan Shaikh
furquan@google.com
Comment-In-Reply-To: Subrata Banik
subrata.banik@intel.com
Comment-In-Reply-To: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-MessageType: comment