[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Move GPIO PM configuration to soc level

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37685 )

Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... 
File src/soc/intel/cannonlake/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... 
PS5, Line 79: /* Enable GPIO PM */
            : 				_SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
> if we only need to decide between 0 or 0x3f then we can avoid NVS and do the required changes in _PT […]

@Duncan,
Do you know if _MPTS and _MWAK is getting called during runtime suspend flow as well. Kane has brought a point that those functions are not getting called during runtime idle and he might need to set those 0-5 bits in runtime idle entry as well