Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33196 )
Change subject: siemens/mc_apl5: Change PTN interface settings ......................................................................
siemens/mc_apl5: Change PTN interface settings
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 1 file changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index c0770f3..f6fed97 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -76,7 +76,8 @@ return (PTN_BUS_ERROR | status); /* Set up configuration data according to the hwinfo block we get. */ cfg.dp_interface_ctrl = 0; - cfg.lvds_interface_ctrl1 = 0x00; + /* Drive LVDS clock for single mode on odd bus per default. */ + cfg.lvds_interface_ctrl1 = 0x01; if (disp_con == PF_DISPLCON_LVDS_DUAL) /* Turn on dual LVDS lane and clock. */ cfg.lvds_interface_ctrl1 |= 0x0b;