[coreboot-gerrit] [S] Change in coreboot[main]: cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78609?usp=email )

Change subject: cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL
......................................................................

cpu/intel/model_206ax: Program Ivy Bridge defaults for MSR_PKGC_IRTL

Ivy Bridge has lower latencies than Sandy Bridge has. Update MSRs
MSR_PKGC_IRTL with values from BWG.

Test: Lenovo X220 still boots.

Change-Id: Ib307e3b191ba68e016cc348f82e2dccf1dc9ae16
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78609
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/cpu/intel/model_206ax/model_206ax_init.c
1 file changed, 12 insertions(+), 3 deletions(-)

Approvals:
  Arthur Heymans: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index cdec3a6..8a4dd3f 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -190,17 +190,26 @@

/* C3 Interrupt Response Time Limit */
    	msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+		if (IS_IVY_CPU(cpu_get_cpuid()))
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x3b;
+		else
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
    	wrmsr(MSR_PKGC3_IRTL, msr);

/* C6 Interrupt Response Time Limit */
    	msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+		if (IS_IVY_CPU(cpu_get_cpuid()))
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+		else
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
    	wrmsr(MSR_PKGC6_IRTL, msr);

/* C7 Interrupt Response Time Limit */
    	msr.hi = 0;
-		msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+		if (IS_IVY_CPU(cpu_get_cpuid()))
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x57;
+		else
+			msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
    	wrmsr(MSR_PKGC7_IRTL, msr);

/* Primary Plane Current Limit (Icc) */