Name of user not set #1002358 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33234 )
Change subject: security/intel/stm STM support ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/33234/1/src/security/intel/stm/Kconfig File src/security/intel/stm/Kconfig:
https://review.coreboot.org/#/c/33234/1/src/security/intel/stm/Kconfig@7 PS1, Line 7: depends on (PLATFORM_USES_FSP2_0||PLATFORM_USES_FSP1_1||PLATFORM_USES_FSP1_0)
why do you need FSP for that?
the FSP depends were suggested (on the original change that is split in this submission) by Philipp Deppenwiese to have this change be effective for all Intel processors.
https://review.coreboot.org/#/c/33234/1/src/security/intel/stm/Kconfig@12 PS1, Line 12: hex "mseg size"
if this is user configureable, what are good values? […]
generally 1MB should suffice for a STM only application and 3MB+ depending upon the size of the VM/PE that is used
https://review.coreboot.org/#/c/33234/1/src/security/intel/stm/StmPlatformRe... File src/security/intel/stm/StmPlatformResource.c:
https://review.coreboot.org/#/c/33234/1/src/security/intel/stm/StmPlatformRe... PS1, Line 180: // Find max bus number and PCIEX length
remove commented code
This is part of the code that is generating the access list for the SMI handler. What needs to be resolved here is how to determine the PCI Express Base address (PcdGet64(...)) in the Coreboot environment then I can fix that function.