Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42189 )
Change subject: nb/intel/gm45: Use PCI bitwise ops ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/early_reset.c:
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... PS3, Line 43: MCHBAR32(DCC_MCHBAR) = : (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
no 😊 […]
Done
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/pcie.c:
https://review.coreboot.org/c/coreboot/+/42189/3/src/northbridge/intel/gm45/... PS3, Line 217: 0x01 << 29
Sure, and the same thing for the 0x03 next to it. […]
Ack