[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add common PSP support

[Felix Held (Code Review)]

Hello Marshall Dawson, Marshall Dawson, Eric Peers,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/40296

to review the following change.

Change subject: soc/amd/picasso: Add common PSP support
......................................................................

soc/amd/picasso: Add common PSP support

Add a new psp.c file so the base address can be determined, and select
the common/block/psp feature.

Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea
Signed-off-by: Marshall Dawson 
Reviewed-on: https://chromium-review.googlesource.com/2020368
Tested-by: Eric Peers 
Reviewed-by: Eric Peers 
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
A src/soc/amd/picasso/psp.c
3 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/40296/1

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index d9211b4..5ea02f1 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -47,6 +47,7 @@
    select SOC_AMD_COMMON_BLOCK_HDA
    select SOC_AMD_COMMON_BLOCK_SATA
    select SOC_AMD_COMMON_BLOCK_SMBUS
+	select SOC_AMD_COMMON_BLOCK_PSP
    select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
    select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
    select PARALLEL_MP
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 2f4f00b..b79f627 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -44,6 +44,7 @@
 romstage-y += southbridge.c
 romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 romstage-y += soc_util.c
+romstage-y += psp.c

verstage-y += gpio.c
 verstage-y += i2c.c
@@ -76,6 +77,7 @@
 ramstage-y += tsc_freq.c
 ramstage-y += finalize.c
 ramstage-y += soc_util.c
+ramstage-y += psp.c

all-y += reset.c

@@ -84,6 +86,7 @@
 smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 smm-y += gpio.c
+smm-y += psp.c

CPPFLAGS_common += -I$(src)/soc/amd/picasso
 CPPFLAGS_common += -I$(src)/soc/amd/picasso/include
diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c
new file mode 100644
index 0000000..9780627
--- /dev/null
+++ b/src/soc/amd/picasso/psp.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <amdblocks/psp.h>
+
+#define PSP_MAILBOX_OFFSET		0x10570
+#define MSR_CU_CBBCFG			0xc00110a2
+
+void *soc_get_mbox_address(void)
+{
+	uintptr_t psp_mmio;
+
+	psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
+	if (psp_mmio == 0xffffffff) {
+		printk(BIOS_WARNING, "PSP: MSR value uninitialized\n");
+		return 0;
+	}
+
+	return (void *)(psp_mmio + PSP_MAILBOX_OFFSET);
+}