[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Update chipset.cb for TSCC and USB

[EricR Lai (Code Review)]

Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48793

to look at the new patch set (#3).

Change subject: soc/intel/alderlake: Update chipset.cb for TSCC and USB
......................................................................

soc/intel/alderlake: Update chipset.cb for TSCC and USB

Refer TGL to add alias for TCSS and USB ports.

Signed-off-by: Eric Lai 
Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chipset.cb
2 files changed, 96 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/48793/3