[coreboot-gerrit] Change in coreboot[master]: armv7: mmu: Use 'tlbimva' to invalidate TLB entries

[Julius Werner (Code Review)]

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43137 )

Change subject: armv7: mmu: Use 'tlbimva' to invalidate TLB entries
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armv7: mmu: Use 'tlbimva' to invalidate TLB entries

The tlbimvaa operation (invalidate unified TLB by MVA, all address
space identifiers) is only available on armv7 processors that support
Multiprocessing Extensions. When used on processors that do not support
the extensions it causes an "undefined instruction" exception.

This patch changes the MMU table entry filling code to use the tlbimva
(invalidate unified TLB entry by MVA and address space identifier)
operation for invalidating TLB entries, which is supported on all armv7
processors.

As address space identifiers are not used in TLB entries in coreboot
(all entries are set as global), these two operations can safely be
used interchangeably. The ASID value supplied to the operation is not
checked for global TLB entries.

More information as well as the data formats for the tlbimvaa and
tlbimva operations are detailed in the "ARM Architecture Reference
Manual ARMv7-A" edition, issue "C.c" page B4-1747.

TEST: Booted Beaglebone Black (my current in progress port)

Change-Id: Ie7dfb4adab20dc7eecb1b20aa2ee6355215a1521
Signed-off-by: Sam Lewis 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43137
Tested-by: build bot (Jenkins) 
Reviewed-by: Julius Werner 
---
M src/arch/arm/armv7/mmu.c
M src/arch/arm/include/armv7/arch/cache.h
2 files changed, 5 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index d823c61..51b4860 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -118,7 +118,7 @@

/* Invalidate the TLB entries. */
    for (i = start_idx; i < end_idx; i++)
-		tlbimvaa(offset + (i << shift));
+		tlbimva(offset + (i << shift));
    dsb();
    isb();
 }
@@ -152,7 +152,7 @@
    *pgd_entry = (pte_t)(uintptr_t)table | ATTR_NEXTLEVEL;
    dccmvac((uintptr_t)pgd_entry);
    dsb();
-	tlbimvaa(start_addr);
+	tlbimva(start_addr);
    dsb();
    isb();

diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index 600ec46..e332c31 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -73,10 +73,10 @@
    asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
 }

-/* invalidate unified TLB by MVA, all ASID */
-static inline void tlbimvaa(unsigned long mva)
+/* invalidate unified TLB by MVA and ASID */
+static inline void tlbimva(unsigned long mva)
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
+	asm volatile ("mcr p15, 0, %0, c8, c7, 1" : : "r" (mva) : "memory");
 }

/* write data access control register (DACR) */