[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40841 )

Change subject: soc/intel/icelake: Fix 16-bit read/write PCI_COMMAND register
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Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40841/3//COMMIT_MSG@7 
PS3, Line 7: Fix 
"Fix" resembles some issue exist and hence this CL has introduced, is there any real issue behind this modification or just optimization ?