[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Set controller state to active in GSPI init

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Usha P, V Sowmya, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34449

to look at the new patch set (#7).

Change subject: soc/intel/common: Set controller state to active in GSPI init
......................................................................

soc/intel/common: Set controller state to active in GSPI init

Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.

BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
     sequence for CML and ICL platforms.

Signed-off-by: Meera Ravindranath 
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34449/7