[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Ravishankar Sarawadi, Tarun, Utkarsh H Patel.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email )

Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
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Patch Set 6:

(2 comments)

Patchset:

PS6:
> This change is not part of any doc, but I will let you if could get some reference.

If there is any change in register definitions between ES and QS, that has to be documented somewhere. we can't/shouldn't program/change the offsets w/o any backing from Intel EDS at minimum.
> Yes this is to do with new revisions coming in with Prod SOC.

How should i review this code to know if those addresses are valid and purposeful as ES soc? also, what is the reason for changing those address space ?  is there any TBT IP revision change between pre-prod and prod SoC ?

File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl:

https://review.coreboot.org/c/coreboot/+/78163/comment/17e1bff6_8a4e27d9 :
PS6, Line 3: 0xC00
> 0xC00 is size increase to access higher offsets so IMO no need to wrap under config.

0xc00 in bytes is the size of the opregion that you have created. hence, my question is if the size 0xc00 is even applicable for pre-prod soc? as you can see the opregion is system memory type and these IPs are using flat/consecutive/linear address space hence, i wish to make sure that you are not entering into the MMIO space of any other IP wrongly.

If you can confirm the size of this IP address space is 0xc00 irrespective of pre-prod and prod, i believe we should be okay here.