[coreboot-gerrit] [S] Change in coreboot[main]: util/cbfstool: Place XIP components and FIT at high flash addresses

[Angel Pons (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Ronak Kanabar, Shuo Liu, Tim Chu, Yu-Ping Wu.

Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email )

Change subject: util/cbfstool: Place XIP components and FIT at high flash addresses
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Patch Set 8:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86570/comment/0944b8d6_fd33c19e?usp... :
PS8, Line 9: CACHE_ROM_SIZE
> I don't get the problem. Of course it can be grown arbitrarily. […]

Does GNR not support caching more than 16 MiB of flash?

https://review.coreboot.org/c/coreboot/+/86570/comment/57c7dabc_798accd8?usp... :
PS8, Line 17: Select XIP_AT_HIGH_ADDR for intel Granite Rapids SoC.
What is the impact of this change? Faster boot times?