Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35516 )
Change subject: device/pci: Ensure full 16-bit VGA port i/o decoding ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35516/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35516/1//COMMIT_MSG@17 PS1, Line 17: these days, so nobody noticed.
It could be that even when implemented for PCIe root ports, CTL_VGA bits for those bridges have no effect when IGD is enabled.
IIRC, they have an effect: the wrath of resource conflicts. This is why we have a .disable op that should be implemented for the IGD.
We should also make sure only one PCIe root port will have CTL_VGA set.
We already do that implicitly. We enable it only on the path to the winning device in set_vga_bridge_bits().
src/soc/intel/common/block/pcie/pcie.c: pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
Unconditionally setting 'ISA enable' bit is also.. interesting.
Yeah, interesting. We try to avoid allocating in those ranges (I learned today) device.c:400 (should work as long as the resource is <= 0x100). But same as the VGA avoidance below it, it won't be noticed by static/preallocated resources. oh wait, nvm, is that an `else if`? dead branch?